Lines Matching +full:imx93 +full:- +full:edma3
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
26 - fsl,imx93-edma3
27 - fsl,imx93-edma4
28 - fsl,imx95-edma5
29 - items:
30 - const: fsl,ls1028a-edma
31 - const: fsl,vf610-edma
41 interrupt-names:
45 "#dma-cells":
56 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h
58 - 2
59 - 3
61 dma-channels:
69 clock-names:
73 power-domains:
80 big-endian:
87 - "#dma-cells"
88 - compatible
89 - reg
90 - interrupts
91 - dma-channels
94 - $ref: dma-controller.yaml#
95 - if:
100 - fsl,imx8qm-edma
101 - fsl,imx93-edma3
102 - fsl,imx93-edma4
103 - fsl,imx95-edma5
106 "#dma-cells":
111 interrupt-names: false
112 clock-names:
114 - const: dma
118 - if:
122 const: fsl,vf610-edma
128 clock-names:
130 - const: dmamux0
131 - const: dmamux1
135 interrupt-names:
137 - const: edma-tx
138 - const: edma-err
142 "#dma-cells":
144 dma-channels:
147 - if:
151 const: fsl,imx7ulp-edma
157 clock-names:
159 - const: dma
160 - const: dmamux0
167 "#dma-cells":
169 dma-channels:
172 - if:
176 const: fsl,imx8ulp-edma
181 clock-names:
185 - const: dma
186 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
188 interrupt-names: false
191 "#dma-cells":
194 - if:
199 - fsl,vf610-edma
200 - fsl,imx7ulp-edma
201 - fsl,imx93-edma3
202 - fsl,imx93-edma4
203 - fsl,imx95-edma5
204 - fsl,imx8ulp-edma
205 - fsl,ls1028a-edma
208 - clocks
210 - if:
215 - fsl,imx8qm-adma
216 - fsl,imx8qm-edma
219 - power-domains
222 power-domains: false
227 - |
228 #include <dt-bindings/interrupt-controller/arm-gic.h>
229 #include <dt-bindings/clock/vf610-clock.h>
231 edma0: dma-controller@40018000 {
232 #dma-cells = <2>;
233 compatible = "fsl,vf610-edma";
239 interrupt-names = "edma-tx", "edma-err";
240 dma-channels = <32>;
241 clock-names = "dmamux0", "dmamux1";
245 - |
246 #include <dt-bindings/interrupt-controller/arm-gic.h>
247 #include <dt-bindings/clock/imx7ulp-clock.h>
249 edma1: dma-controller@40080000 {
250 #dma-cells = <2>;
251 compatible = "fsl,imx7ulp-edma";
254 dma-channels = <32>;
271 /* last is eDMA2-ERR interrupt */
273 clock-names = "dma", "dmamux0";
277 - |
278 #include <dt-bindings/interrupt-controller/arm-gic.h>
279 #include <dt-bindings/firmware/imx/rsrc.h>
281 dma-controller@5a9f0000 {
282 compatible = "fsl,imx8qm-edma";
284 #dma-cells = <3>;
285 dma-channels = <8>;
294 power-domains = <&pd IMX_SC_R_DMA_3_CH0>,