Lines Matching +full:fifo +full:- +full:width

1 Analog Devices AXI-DMAC DMA controller
4  - compatible: Must be "adi,axi-dmac-1.00.a".
5  - reg: Specification for the controllers memory mapped register map.
6  - interrupts: Specification for the controllers interrupt.
7  - clocks: Phandle and specifier to the controllers AXI interface clock
8  - #dma-cells: Must be 1.
10 Required sub-nodes:
11  - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12    the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
16  - #size-cells: Must be 0
17  - #address-cells: Must be 1
19 Required channel sub-node properties:
20  - reg: Which channel this node refers to.
21  - adi,source-bus-width,
22    adi,destination-bus-width: Width of the source or destination bus in bits.
23  - adi,source-bus-type,
24    adi,destination-bus-type: Type of the source or destination bus. Must be one
28 	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
31  - adi,length-width: Width of the DMA transfer length register.
32  - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
34  - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
37 described in the dma.txt file using a one-cell specifier. The value of the
43 	compatible = "adi,axi-dmac-1.00.a";
47 	#dma-cells = <1>;
50 		#size-cells = <0>;
51 		#address-cells = <1>;
53 		dma-channel@0 {
55 			adi,source-bus-width = <32>;
56 			adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
57 			adi,destination-bus-width = <64>;
58 			adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;