Lines Matching +full:tegra20 +full:- +full:dsi
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^vi@[0-9a-f]+$"
19 - const: nvidia,tegra20-vi
20 - const: nvidia,tegra30-vi
21 - const: nvidia,tegra114-vi
22 - const: nvidia,tegra124-vi
23 - items:
24 - const: nvidia,tegra132-vi
25 - const: nvidia,tegra124-vi
26 - const: nvidia,tegra210-vi
27 - const: nvidia,tegra186-vi
28 - const: nvidia,tegra194-vi
41 - description: module reset
43 reset-names:
45 - const: vi
54 interconnect-names:
58 operating-points-v2: true
60 power-domains:
62 - description: phandle to the VENC power domain
64 "#address-cells":
67 "#size-cells":
73 avdd-dsi-csi-supply:
74 description: DSI/CSI power supply. Must supply 1.2 V.
77 $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml
89 "^csi@[0-9a-f]+$":
95 - compatible
96 - reg
97 - interrupts
98 - clocks
101 - if:
106 - nvidia,tegra20-vi
107 - nvidia,tegra30-vi
108 - nvidia,tegra114-vi
109 - nvidia,tegra124-vi
112 - resets
113 - reset-names
116 - power-domains
119 - |
120 #include <dt-bindings/clock/tegra20-car.h>
121 #include <dt-bindings/interrupt-controller/arm-gic.h>
124 #address-cells = <1>;
125 #size-cells = <0>;
133 remote-endpoint = <&vi_vip_in>;
140 compatible = "nvidia,tegra20-vi";
145 reset-names = "vi";
148 compatible = "nvidia,tegra20-vip";
150 #address-cells = <1>;
151 #size-cells = <0>;
155 remote-endpoint = <&mt9v111_out>;
161 remote-endpoint = <&vi_in>;
168 #address-cells = <1>;
169 #size-cells = <0>;
173 remote-endpoint = <&vi_vip_out>;
179 - |
180 #include <dt-bindings/clock/tegra210-car.h>
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 compatible = "nvidia,tegra210-vi";
187 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
188 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
191 power-domains = <&pd_venc>;
193 #address-cells = <1>;
194 #size-cells = <1>;
199 compatible = "nvidia,tegra210-csi";
201 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
205 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
208 assigned-clock-rates = <102000000>,
218 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
219 power-domains = <&pd_sor>;