Lines Matching +full:dma +full:- +full:window
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
25 '#size-cells':
38 clock-names:
44 - description: display hub reset
45 - description: window group 0 reset
46 - description: window group 1 reset
47 - description: window group 2 reset
48 - description: window group 3 reset
49 - description: window group 4 reset
50 - description: window group 5 reset
52 reset-names:
54 - const: misc
55 - const: wgrp0
56 - const: wgrp1
57 - const: wgrp2
58 - const: wgrp3
59 - const: wgrp4
60 - const: wgrp5
62 power-domains:
69 "^display@[0-9a-f]+$":
73 - if:
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
84 - description: display hub clock
86 clock-names:
88 - const: disp
89 - const: dsc
90 - const: hub
95 - description: display core clock
96 - description: display hub clock
98 clock-names:
100 - const: disp
101 - const: hub
106 - compatible
107 - reg
108 - clocks
109 - clock-names
110 - resets
111 - reset-names
112 - power-domains
113 - "#address-cells"
114 - "#size-cells"
115 - ranges
118 - |
119 #include <dt-bindings/clock/tegra186-clock.h>
120 #include <dt-bindings/interrupt-controller/arm-gic.h>
121 #include <dt-bindings/memory/tegra186-mc.h>
122 #include <dt-bindings/power/tegra186-powergate.h>
123 #include <dt-bindings/reset/tegra186-reset.h>
125 display-hub@15200000 {
126 compatible = "nvidia,tegra186-display";
135 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
140 clock-names = "disp", "dsc", "hub";
142 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
144 #address-cells = <1>;
145 #size-cells = <1>;
150 compatible = "nvidia,tegra186-dc";
154 clock-names = "dc";
156 reset-names = "dc";
158 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
161 interconnect-names = "dma-mem", "read-1";
169 compatible = "nvidia,tegra186-dc";
173 clock-names = "dc";
175 reset-names = "dc";
177 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
180 interconnect-names = "dma-mem", "read-1";
188 compatible = "nvidia,tegra186-dc";
192 clock-names = "dc";
194 reset-names = "dc";
196 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
199 interconnect-names = "dma-mem", "read-1";
207 - |
208 #include <dt-bindings/clock/tegra194-clock.h>
209 #include <dt-bindings/interrupt-controller/arm-gic.h>
210 #include <dt-bindings/memory/tegra194-mc.h>
211 #include <dt-bindings/power/tegra194-powergate.h>
212 #include <dt-bindings/reset/tegra194-reset.h>
214 display-hub@15200000 {
215 compatible = "nvidia,tegra194-display";
224 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
228 clock-names = "disp", "hub";
230 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
232 #address-cells = <1>;
233 #size-cells = <1>;
238 compatible = "nvidia,tegra194-dc";
242 clock-names = "dc";
244 reset-names = "dc";
246 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
249 interconnect-names = "dma-mem", "read-1";
256 compatible = "nvidia,tegra194-dc";
260 clock-names = "dc";
262 reset-names = "dc";
264 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
267 interconnect-names = "dma-mem", "read-1";
274 compatible = "nvidia,tegra194-dc";
278 clock-names = "dc";
280 reset-names = "dc";
282 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
285 interconnect-names = "dma-mem", "read-1";
292 compatible = "nvidia,tegra194-dc";
296 clock-names = "dc";
298 reset-names = "dc";
300 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
303 interconnect-names = "dma-mem", "read-1";