Lines Matching +full:px30 +full:- +full:power

5 - compatible: matching the soc type, one of
6 	- "rockchip,rk3288-lvds";
7 	- "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 	clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
17 - avdd3v3-supply: regulator phandle for 3.3V analog power
19 - rockchip,grf: phandle to the general register files syscon
20 - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
22 - phys: LVDS/DSI DPHY (px30 only)
23 - phy-names: name of the PHY, must be "dphy" (px30 only)
26 - pinctrl-names: must contain a "lcdc" entry.
27 - pinctrl-0: pin control group to be used for this controller.
32 	Documentation/devicetree/bindings/media/video-interfaces.txt
36 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
37 - video port 1 for either a panel or subsequent encoder
41 lvds_panel: lvds-panel {
43 	enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
44 	data-mapping = "jeida-24";
48 			remote-endpoint = <&lvds_out_panel>;
56 		compatible = "rockchip,rk3288-lvds";
60 		clock-names = "pclk_lvds";
61 		pinctrl-names = "lcdc";
62 		pinctrl-0 = <&lcdc_ctl>;
63 		avdd1v0-supply = <&vdd10_lcd>;
64 		avdd1v8-supply = <&vcc18_lcd>;
65 		avdd3v3-supply = <&vcca_33>;
68 			#address-cells = <1>;
69 			#size-cells = <0>;
76 					remote-endpoint = <&vopb_out_lvds>;
80 					remote-endpoint = <&vopl_out_lvds>;
88 					remote-endpoint = <&panel_in_lvds>;