Lines Matching +full:phy +full:- +full:i2c
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Yao <markyao0591@gmail.com>
14 with a companion PHY IP.
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
25 - rockchip,rk3399-dw-hdmi
26 - rockchip,rk3568-dw-hdmi
28 reg-io-width:
31 avdd-0v9-supply:
37 avdd-1v8-supply:
45 - {}
46 - {}
49 - description: The HDMI CEC controller main clock
50 - description: Power for GRF IO
51 - description: External clock for some HDMI PHY (old clock name, deprecated)
52 - description: External clock for some HDMI PHY (new name)
54 clock-names:
57 - {}
58 - {}
59 - enum:
60 - cec
61 - grf
62 - vpll
63 - ref
64 - enum:
65 - grf
66 - vpll
67 - ref
68 - enum:
69 - vpll
70 - ref
72 ddc-i2c-bus:
75 The HDMI DDC bus can be connected to either a system I2C master or the
76 functionally-reduced I2C master contained in the DWC HDMI. When connected
77 to a system I2C master this property contains a phandle to that I2C
82 description: The HDMI PHY
84 phy-names:
87 pinctrl-names:
90 intended to work around a hardware errata that can cause the DDC I2C
94 - const: default
95 - const: unwedge
122 - compatible
123 - reg
124 - reg-io-width
125 - clocks
126 - clock-names
127 - interrupts
128 - ports
129 - rockchip,grf
134 - |
135 #include <dt-bindings/clock/rk3288-cru.h>
136 #include <dt-bindings/interrupt-controller/arm-gic.h>
137 #include <dt-bindings/interrupt-controller/irq.h>
140 compatible = "rockchip,rk3288-dw-hdmi";
142 reg-io-width = <4>;
143 ddc-i2c-bus = <&i2c5>;
147 clock-names = "iahb", "isfr";
151 #address-cells = <1>;
152 #size-cells = <0>;
156 remote-endpoint = <&vopb_out_hdmi>;
160 remote-endpoint = <&vopl_out_hdmi>;