Lines Matching +full:rk3399 +full:- +full:cru

1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 	       Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
20 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
22 - rockchip,grf: this soc should set GRF regs, so need get grf here.
24 - ports: contain a port nodes with endpoint definitions as defined in
25 	 Documentation/devicetree/bindings/media/video-interfaces.txt.
28 - phys: from general PHY binding: the phandle for the PHY device.
30 - extcon: extcon specifier for the Power Delivery
32 - #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
34 -------------------------------------------------------------------------------
38 		compatible = "rockchip,rk3399-cdn-dp";
41 		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
42 			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
43 		clock-names = "core-clk", "pclk", "spdif", "grf";
44 		assigned-clocks = <&cru SCLK_DP_CORE>;
45 		assigned-clock-rates = <100000000>;
46 		power-domains = <&power RK3399_PD_HDCP>;
48 		resets = <&cru SRST_DPTX_SPDIF_REC>;
49 		reset-names = "spdif";
52 		#address-cells = <1>;
53 		#size-cells = <0>;
54 		#sound-dai-cells = <1>;
57 			#address-cells = <1>;
58 			#size-cells = <0>;
61 				#address-cells = <1>;
62 				#size-cells = <0>;
65 					remote-endpoint = <&vopb_out_dp>;
70 					remote-endpoint = <&vopl_out_dp>;