Lines Matching +full:displayport +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8750-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
33 - description: Interconnect path from mdp0 port to the data bus
34 - description: Interconnect path from CPU to the reg bus
36 interconnect-names:
38 - const: mdp0-mem
39 - const: cpu-cfg
42 "^display-controller@[0-9a-f]+$":
47 const: qcom,sm8750-dpu
49 "^displayport-controller@[0-9a-f]+$":
55 const: qcom,sm8750-dp
57 "^dsi@[0-9a-f]+$":
63 const: qcom,sm8750-dsi-ctrl
65 "^phy@[0-9a-f]+$":
70 const: qcom,sm8750-dsi-phy-3nm
73 - compatible
78 - |
79 #include <dt-bindings/clock/qcom,rpmh.h>
80 #include <dt-bindings/interconnect/qcom,icc.h>
81 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
82 #include <dt-bindings/interrupt-controller/arm-gic.h>
83 #include <dt-bindings/phy/phy-qcom-qmp.h>
84 #include <dt-bindings/power/qcom,rpmhpd.h>
86 display-subsystem@ae00000 {
87 compatible = "qcom,sm8750-mdss";
89 reg-names = "mdss";
101 interconnect-names = "mdp0-mem",
102 "cpu-cfg";
106 power-domains = <&mdss_gdsc>;
110 interrupt-controller;
111 #interrupt-cells = <1>;
113 #address-cells = <1>;
114 #size-cells = <1>;
117 display-controller@ae01000 {
118 compatible = "qcom,sm8750-dpu";
121 reg-names = "mdp",
124 interrupts-extended = <&mdss 0>;
131 clock-names = "nrt_bus",
137 assigned-clocks = <&disp_cc_mdss_vsync_clk>;
138 assigned-clock-rates = <19200000>;
140 operating-points-v2 = <&mdp_opp_table>;
142 power-domains = <&rpmhpd RPMHPD_MMCX>;
145 #address-cells = <1>;
146 #size-cells = <0>;
152 remote-endpoint = <&mdss_dsi0_in>;
160 remote-endpoint = <&mdss_dsi1_in>;
168 remote-endpoint = <&mdss_dp0_in>;
173 mdp_opp_table: opp-table {
174 compatible = "operating-points-v2";
176 opp-207000000 {
177 opp-hz = /bits/ 64 <207000000>;
178 required-opps = <&rpmhpd_opp_low_svs>;
181 opp-337000000 {
182 opp-hz = /bits/ 64 <337000000>;
183 required-opps = <&rpmhpd_opp_svs>;
186 opp-417000000 {
187 opp-hz = /bits/ 64 <417000000>;
188 required-opps = <&rpmhpd_opp_svs_l1>;
191 opp-532000000 {
192 opp-hz = /bits/ 64 <532000000>;
193 required-opps = <&rpmhpd_opp_nom>;
196 opp-575000000 {
197 opp-hz = /bits/ 64 <575000000>;
198 required-opps = <&rpmhpd_opp_nom_l1>;
204 compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
206 reg-names = "dsi_ctrl";
208 interrupts-extended = <&mdss 4>;
222 clock-names = "byte",
235 operating-points-v2 = <&mdss_dsi_opp_table>;
237 power-domains = <&rpmhpd RPMHPD_MMCX>;
240 phy-names = "dsi";
242 vdda-supply = <&vreg_l3g_1p2>;
244 #address-cells = <1>;
245 #size-cells = <0>;
248 #address-cells = <1>;
249 #size-cells = <0>;
255 remote-endpoint = <&dpu_intf1_out>;
263 remote-endpoint = <&panel0_in>;
264 data-lanes = <0 1 2 3>;
269 mdss_dsi_opp_table: opp-table {
270 compatible = "operating-points-v2";
272 opp-187500000 {
273 opp-hz = /bits/ 64 <187500000>;
274 required-opps = <&rpmhpd_opp_low_svs>;
277 opp-300000000 {
278 opp-hz = /bits/ 64 <300000000>;
279 required-opps = <&rpmhpd_opp_svs>;
282 opp-358000000 {
283 opp-hz = /bits/ 64 <358000000>;
284 required-opps = <&rpmhpd_opp_svs_l1>;
290 compatible = "qcom,sm8750-dsi-phy-3nm";
294 reg-names = "dsi_phy",
300 clock-names = "iface",
303 vdds-supply = <&vreg_l3i_0p88>;
305 #clock-cells = <1>;
306 #phy-cells = <0>;
310 compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
312 reg-names = "dsi_ctrl";
314 interrupts-extended = <&mdss 5>;
328 clock-names = "byte",
341 operating-points-v2 = <&mdss_dsi_opp_table>;
343 power-domains = <&rpmhpd RPMHPD_MMCX>;
346 phy-names = "dsi";
348 #address-cells = <1>;
349 #size-cells = <0>;
352 #address-cells = <1>;
353 #size-cells = <0>;
359 remote-endpoint = <&dpu_intf2_out>;
373 compatible = "qcom,sm8750-dsi-phy-3nm";
377 reg-names = "dsi_phy",
383 clock-names = "iface",
386 #clock-cells = <1>;
387 #phy-cells = <0>;
390 displayport-controller@af54000 {
391 compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
398 interrupts-extended = <&mdss 12>;
405 clock-names = "core_iface",
411 assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
413 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
416 operating-points-v2 = <&dp_opp_table>;
418 power-domains = <&rpmhpd RPMHPD_MMCX>;
421 phy-names = "dp";
423 #sound-dai-cells = <0>;
425 dp_opp_table: opp-table {
426 compatible = "operating-points-v2";
428 opp-192000000 {
429 opp-hz = /bits/ 64 <192000000>;
430 required-opps = <&rpmhpd_opp_low_svs_d1>;
433 opp-270000000 {
434 opp-hz = /bits/ 64 <270000000>;
435 required-opps = <&rpmhpd_opp_low_svs>;
438 opp-540000000 {
439 opp-hz = /bits/ 64 <540000000>;
440 required-opps = <&rpmhpd_opp_svs_l1>;
443 opp-810000000 {
444 opp-hz = /bits/ 64 <810000000>;
445 required-opps = <&rpmhpd_opp_nom>;
450 #address-cells = <1>;
451 #size-cells = <0>;
457 remote-endpoint = <&dpu_intf0_out>;
465 remote-endpoint = <&usb_dp_qmpphy_dp_in>;