Lines Matching +full:0 +full:x0aeb0000
39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
112 iommus = <&apps_smmu 0x1c00 0x2>;
120 reg = <0x0ae01000 0x8f000>,
121 <0x0aeb0000 0x2008>;
144 interrupts = <0>;
148 #size-cells = <0>;
150 port@0 {
151 reg = <0>;
192 reg = <0x0ae94000 0x400>;
213 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
222 #size-cells = <0>;
226 #size-cells = <0>;
228 port@0 {
229 reg = <0>;
264 reg = <0x0ae95000 0x200>,
265 <0x0ae95200 0x280>,
266 <0x0ae95500 0x400>;
272 #phy-cells = <0>;
281 reg = <0x0ae96000 0x400>;
302 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
311 #size-cells = <0>;
315 #size-cells = <0>;
317 port@0 {
318 reg = <0>;
334 reg = <0x0ae97000 0x200>,
335 <0x0ae97200 0x280>,
336 <0x0ae97500 0x400>;
342 #phy-cells = <0>;