Lines Matching +full:opp +full:- +full:460000000
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm8250-mdss
25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock
27 - description: Display sf axi clock
28 - description: Display core clock
30 clock-names:
32 - const: iface
33 - const: bus
34 - const: nrt_bus
35 - const: core
43 interconnect-names:
47 "^display-controller@[0-9a-f]+$":
53 const: qcom,sm8250-dpu
55 "^displayport-controller@[0-9a-f]+$":
62 - const: qcom,sm8250-dp
63 - const: qcom,sm8350-dp
65 "^dsi@[0-9a-f]+$":
72 - const: qcom,sm8250-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
75 "^phy@[0-9a-f]+$":
81 const: qcom,dsi-phy-7nm
84 - compatible
89 - |
90 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
91 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
92 #include <dt-bindings/clock/qcom,rpmh.h>
93 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #include <dt-bindings/interconnect/qcom,sm8250.h>
95 #include <dt-bindings/power/qcom,rpmhpd.h>
97 display-subsystem@ae00000 {
98 compatible = "qcom,sm8250-mdss";
100 reg-names = "mdss";
104 interconnect-names = "mdp0-mem", "mdp1-mem";
106 power-domains = <&dispcc MDSS_GDSC>;
112 clock-names = "iface", "bus", "nrt_bus", "core";
115 interrupt-controller;
116 #interrupt-cells = <1>;
120 #address-cells = <1>;
121 #size-cells = <1>;
124 display-controller@ae01000 {
125 compatible = "qcom,sm8250-dpu";
128 reg-names = "mdp", "vbif";
134 clock-names = "iface", "bus", "core", "vsync";
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
137 assigned-clock-rates = <19200000>;
139 operating-points-v2 = <&mdp_opp_table>;
140 power-domains = <&rpmhpd RPMHPD_MMCX>;
142 interrupt-parent = <&mdss>;
146 #address-cells = <1>;
147 #size-cells = <0>;
152 remote-endpoint = <&dsi0_in>;
159 remote-endpoint = <&dsi1_in>;
164 mdp_opp_table: opp-table {
165 compatible = "operating-points-v2";
167 opp-200000000 {
168 opp-hz = /bits/ 64 <200000000>;
169 required-opps = <&rpmhpd_opp_low_svs>;
172 opp-300000000 {
173 opp-hz = /bits/ 64 <300000000>;
174 required-opps = <&rpmhpd_opp_svs>;
177 opp-345000000 {
178 opp-hz = /bits/ 64 <345000000>;
179 required-opps = <&rpmhpd_opp_svs_l1>;
182 opp-460000000 {
183 opp-hz = /bits/ 64 <460000000>;
184 required-opps = <&rpmhpd_opp_nom>;
190 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
192 reg-names = "dsi_ctrl";
194 interrupt-parent = <&mdss>;
203 clock-names = "byte",
210 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
212 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
214 operating-points-v2 = <&dsi_opp_table>;
215 power-domains = <&rpmhpd RPMHPD_MMCX>;
218 phy-names = "dsi";
220 #address-cells = <1>;
221 #size-cells = <0>;
224 #address-cells = <1>;
225 #size-cells = <0>;
230 remote-endpoint = <&dpu_intf1_out>;
241 dsi_opp_table: opp-table {
242 compatible = "operating-points-v2";
244 opp-187500000 {
245 opp-hz = /bits/ 64 <187500000>;
246 required-opps = <&rpmhpd_opp_low_svs>;
249 opp-300000000 {
250 opp-hz = /bits/ 64 <300000000>;
251 required-opps = <&rpmhpd_opp_svs>;
254 opp-358000000 {
255 opp-hz = /bits/ 64 <358000000>;
256 required-opps = <&rpmhpd_opp_svs_l1>;
262 compatible = "qcom,dsi-phy-7nm";
266 reg-names = "dsi_phy",
270 #clock-cells = <1>;
271 #phy-cells = <0>;
275 clock-names = "iface", "ref";
276 vdds-supply = <&vreg_dsi_phy>;
280 compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
282 reg-names = "dsi_ctrl";
284 interrupt-parent = <&mdss>;
293 clock-names = "byte",
300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
302 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
304 operating-points-v2 = <&dsi_opp_table>;
305 power-domains = <&rpmhpd RPMHPD_MMCX>;
308 phy-names = "dsi";
310 #address-cells = <1>;
311 #size-cells = <0>;
314 #address-cells = <1>;
315 #size-cells = <0>;
320 remote-endpoint = <&dpu_intf2_out>;
333 compatible = "qcom,dsi-phy-7nm";
337 reg-names = "dsi_phy",
341 #clock-cells = <1>;
342 #phy-cells = <0>;
346 clock-names = "iface", "ref";
347 vdds-supply = <&vreg_dsi_phy>;