Lines Matching +full:dispcc +full:- +full:qcm2290
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm6115-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AXI clock
27 - description: Display core clock
34 - description: Interconnect path from mdp0 port to the data bus
35 - description: Interconnect path from CPU to the reg bus
37 interconnect-names:
39 - const: mdp0-mem
40 - const: cpu-cfg
43 "^display-controller@[0-9a-f]+$":
49 const: qcom,sm6115-dpu
51 "^dsi@[0-9a-f]+$":
58 - items:
59 - const: qcom,sm6115-dsi-ctrl
60 - const: qcom,mdss-dsi-ctrl
61 - description: Old binding, please don't use
63 const: qcom,dsi-ctrl-6g-qcm2290
65 "^phy@[0-9a-f]+$":
71 const: qcom,dsi-phy-14nm-2290
74 - compatible
79 - |
80 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
81 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
82 #include <dt-bindings/clock/qcom,rpmcc.h>
83 #include <dt-bindings/interrupt-controller/arm-gic.h>
84 #include <dt-bindings/power/qcom-rpmpd.h>
86 display-subsystem@5e00000 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "qcom,sm6115-mdss";
91 reg-names = "mdss";
92 power-domains = <&dispcc MDSS_GDSC>;
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
105 display-controller@5e01000 {
106 compatible = "qcom,sm6115-dpu";
109 reg-names = "mdp", "vbif";
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_MDP_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_ROT_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
117 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
119 operating-points-v2 = <&mdp_opp_table>;
120 power-domains = <&rpmpd SM6115_VDDCX>;
122 interrupt-parent = <&mdss>;
126 #address-cells = <1>;
127 #size-cells = <0>;
132 remote-endpoint = <&dsi0_in>;
139 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
141 reg-names = "dsi_ctrl";
143 interrupt-parent = <&mdss>;
146 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
147 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
148 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
149 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
150 <&dispcc DISP_CC_MDSS_AHB_CLK>,
152 clock-names = "byte",
158 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
159 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
161 operating-points-v2 = <&dsi_opp_table>;
162 power-domains = <&rpmpd SM6115_VDDCX>;
165 #address-cells = <1>;
166 #size-cells = <0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
175 remote-endpoint = <&dpu_intf1_out>;
188 compatible = "qcom,dsi-phy-14nm-2290";
192 reg-names = "dsi_phy",
196 #clock-cells = <1>;
197 #phy-cells = <0>;
199 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
200 clock-names = "iface", "ref";