Lines Matching +full:displayport +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <lumag@kernel.org>
13 SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sar2130p-mdss
24 - description: Display MDSS AHB
25 - description: Display AHB
26 - description: Display hf AXI
27 - description: Display core
34 - description: Interconnect path from mdp0 port to the data bus
35 - description: Interconnect path from CPU to the reg bus
37 interconnect-names:
39 - const: mdp0-mem
40 - const: cpu-cfg
43 "^display-controller@[0-9a-f]+$":
48 const: qcom,sar2130p-dpu
50 "^displayport-controller@[0-9a-f]+$":
56 const: qcom,sar2130p-dp
58 "^dsi@[0-9a-f]+$":
64 const: qcom,sar2130p-dsi-ctrl
66 "^phy@[0-9a-f]+$":
71 const: qcom,sar2130p-dsi-phy-5nm
74 - compatible
79 - |
80 #include <dt-bindings/interrupt-controller/arm-gic.h>
81 #include <dt-bindings/power/qcom,rpmhpd.h>
82 #include <dt-bindings/phy/phy-qcom-qmp.h>
84 display-subsystem@ae00000 {
85 compatible = "qcom,sar2130p-mdss";
87 reg-names = "mdss";
91 interconnect-names = "mdp0-mem", "cpu-cfg";
95 power-domains = <&dispcc_mdss_gdsc>;
101 clock-names = "iface", "bus", "nrt_bus", "core";
104 interrupt-controller;
105 #interrupt-cells = <1>;
109 #address-cells = <1>;
110 #size-cells = <1>;
113 display-controller@ae01000 {
114 compatible = "qcom,sar2130p-dpu";
117 reg-names = "mdp", "vbif";
125 clock-names = "bus",
132 assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>;
133 assigned-clock-rates = <19200000>;
135 operating-points-v2 = <&mdp_opp_table>;
136 power-domains = <&rpmhpd RPMHPD_MMCX>;
138 interrupt-parent = <&mdss>;
142 #address-cells = <1>;
143 #size-cells = <0>;
149 remote-endpoint = <&mdss_dp0_in>;
157 remote-endpoint = <&mdss_dsi0_in>;
165 remote-endpoint = <&mdss_dsi1_in>;
170 mdp_opp_table: opp-table {
171 compatible = "operating-points-v2";
173 opp-200000000 {
174 opp-hz = /bits/ 64 <200000000>;
175 required-opps = <&rpmhpd_opp_low_svs>;
178 opp-325000000 {
179 opp-hz = /bits/ 64 <325000000>;
180 required-opps = <&rpmhpd_opp_svs>;
183 opp-375000000 {
184 opp-hz = /bits/ 64 <375000000>;
185 required-opps = <&rpmhpd_opp_svs_l1>;
188 opp-514000000 {
189 opp-hz = /bits/ 64 <514000000>;
190 required-opps = <&rpmhpd_opp_nom>;
195 displayport-controller@ae90000 {
196 compatible = "qcom,sar2130p-dp",
197 "qcom,sm8350-dp";
204 interrupt-parent = <&mdss>;
211 clock-names = "core_iface",
217 assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
219 assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
223 phy-names = "dp";
225 #sound-dai-cells = <0>;
227 operating-points-v2 = <&dp_opp_table>;
228 power-domains = <&rpmhpd RPMHPD_MMCX>;
231 #address-cells = <1>;
232 #size-cells = <0>;
237 remote-endpoint = <&dpu_intf0_out>;
244 remote-endpoint = <&usb_dp_qmpphy_dp_in>;
249 dp_opp_table: opp-table {
250 compatible = "operating-points-v2";
252 opp-162000000 {
253 opp-hz = /bits/ 64 <162000000>;
254 required-opps = <&rpmhpd_opp_low_svs_d1>;
257 opp-270000000 {
258 opp-hz = /bits/ 64 <270000000>;
259 required-opps = <&rpmhpd_opp_low_svs>;
262 opp-540000000 {
263 opp-hz = /bits/ 64 <540000000>;
264 required-opps = <&rpmhpd_opp_svs_l1>;
267 opp-810000000 {
268 opp-hz = /bits/ 64 <810000000>;
269 required-opps = <&rpmhpd_opp_nom>;
275 compatible = "qcom,sar2130p-dsi-ctrl",
276 "qcom,mdss-dsi-ctrl";
278 reg-names = "dsi_ctrl";
280 interrupt-parent = <&mdss>;
289 clock-names = "byte",
296 assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>,
298 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
300 operating-points-v2 = <&dsi_opp_table>;
301 power-domains = <&rpmhpd RPMHPD_MMCX>;
304 phy-names = "dsi";
306 #address-cells = <1>;
307 #size-cells = <0>;
310 #address-cells = <1>;
311 #size-cells = <0>;
317 remote-endpoint = <&dpu_intf1_out>;
329 dsi_opp_table: opp-table {
330 compatible = "operating-points-v2";
332 opp-187500000 {
333 opp-hz = /bits/ 64 <187500000>;
334 required-opps = <&rpmhpd_opp_low_svs>;
337 opp-300000000 {
338 opp-hz = /bits/ 64 <300000000>;
339 required-opps = <&rpmhpd_opp_svs>;
342 opp-358000000 {
343 opp-hz = /bits/ 64 <358000000>;
344 required-opps = <&rpmhpd_opp_svs_l1>;
350 compatible = "qcom,sar2130p-dsi-phy-5nm";
354 reg-names = "dsi_phy",
358 #clock-cells = <1>;
359 #phy-cells = <0>;
363 clock-names = "iface", "ref";
367 compatible = "qcom,sar2130p-dsi-ctrl",
368 "qcom,mdss-dsi-ctrl";
370 reg-names = "dsi_ctrl";
372 interrupt-parent = <&mdss>;
381 clock-names = "byte",
388 assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>,
390 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
392 operating-points-v2 = <&dsi_opp_table>;
393 power-domains = <&rpmhpd RPMHPD_MMCX>;
396 phy-names = "dsi";
398 #address-cells = <1>;
399 #size-cells = <0>;
402 #address-cells = <1>;
403 #size-cells = <0>;
409 remote-endpoint = <&dpu_intf2_out>;
423 compatible = "qcom,sar2130p-dsi-phy-5nm";
427 reg-names = "dsi_phy",
431 #clock-cells = <1>;
432 #phy-cells = <0>;
436 clock-names = "iface", "ref";