Lines Matching +full:qcm2290 +full:- +full:dispcc
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Loic Poulain <loic.poulain@linaro.org>
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15 are mentioned for QCM2290 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,qcm2290-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AXI clock
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: bus
33 - const: core
40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CPU to the reg bus
43 interconnect-names:
45 - const: mdp0-mem
46 - const: cpu-cfg
49 "^display-controller@[0-9a-f]+$":
55 const: qcom,qcm2290-dpu
57 "^dsi@[0-9a-f]+$":
64 - const: qcom,qcm2290-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
67 "^phy@[0-9a-f]+$":
73 const: qcom,dsi-phy-14nm-2290
76 - compatible
81 - |
82 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
83 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
84 #include <dt-bindings/clock/qcom,rpmcc.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,qcm2290.h>
87 #include <dt-bindings/power/qcom-rpmpd.h>
89 display-subsystem@5e00000 {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 compatible = "qcom,qcm2290-mdss";
94 reg-names = "mdss";
95 power-domains = <&dispcc MDSS_GDSC>;
98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
99 clock-names = "iface", "bus", "core";
102 interrupt-controller;
103 #interrupt-cells = <1>;
107 interconnect-names = "mdp0-mem",
108 "cpu-cfg";
114 display-controller@5e01000 {
115 compatible = "qcom,qcm2290-dpu";
118 reg-names = "mdp", "vbif";
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_MDP_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
125 clock-names = "bus", "iface", "core", "lut", "vsync";
127 operating-points-v2 = <&mdp_opp_table>;
128 power-domains = <&rpmpd QCM2290_VDDCX>;
130 interrupt-parent = <&mdss>;
134 #address-cells = <1>;
135 #size-cells = <0>;
140 remote-endpoint = <&dsi0_in>;
147 compatible = "qcom,qcm2290-dsi-ctrl",
148 "qcom,mdss-dsi-ctrl";
150 reg-names = "dsi_ctrl";
152 interrupt-parent = <&mdss>;
155 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
156 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
157 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
158 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
159 <&dispcc DISP_CC_MDSS_AHB_CLK>,
161 clock-names = "byte",
167 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
168 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
170 operating-points-v2 = <&dsi_opp_table>;
171 power-domains = <&rpmpd QCM2290_VDDCX>;
174 phy-names = "dsi";
176 #address-cells = <1>;
177 #size-cells = <0>;
180 #address-cells = <1>;
181 #size-cells = <0>;
186 remote-endpoint = <&dpu_intf1_out>;
199 compatible = "qcom,dsi-phy-14nm-2290";
203 reg-names = "dsi_phy",
207 #clock-cells = <1>;
208 #phy-cells = <0>;
210 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
211 clock-names = "iface", "ref";
212 vcca-supply = <&vreg_dsi_phy>;