Lines Matching +full:dispcc +full:- +full:qcm2290

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU on QCM2290
10   - Loic Poulain <loic.poulain@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16     const: qcom,qcm2290-dpu
20       - description: Address offset and size for mdp register set
21       - description: Address offset and size for vbif register set
23   reg-names:
25       - const: mdp
26       - const: vbif
30       - description: Display AXI clock from gcc
31       - description: Display AHB clock from dispcc
32       - description: Display core clock from dispcc
33       - description: Display lut clock from dispcc
34       - description: Display vsync clock from dispcc
36   clock-names:
38       - const: bus
39       - const: iface
40       - const: core
41       - const: lut
42       - const: vsync
45   - compatible
46   - reg
47   - reg-names
48   - clocks
49   - clock-names
54   - |
55     #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
56     #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
57     #include <dt-bindings/power/qcom-rpmpd.h>
59     display-controller@5e01000 {
60         compatible = "qcom,qcm2290-dpu";
63         reg-names = "mdp", "vbif";
66                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
67                  <&dispcc DISP_CC_MDSS_MDP_CLK>,
68                  <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
69                  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
70         clock-names = "bus", "iface", "core", "lut", "vsync";
72         operating-points-v2 = <&mdp_opp_table>;
73         power-domains = <&rpmpd QCM2290_VDDCX>;
75         interrupt-parent = <&mdss>;
79             #address-cells = <1>;
80             #size-cells = <0>;
85                     remote-endpoint = <&dsi0_in>;