Lines Matching +full:gcc +full:- +full:apq8084
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
14 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 - Rob Clark <robdclark@gmail.com>
20 - const: qcom,mdp5
22 - items:
23 - enum:
24 - qcom,apq8084-mdp5
25 - qcom,msm8226-mdp5
26 - qcom,msm8916-mdp5
27 - qcom,msm8917-mdp5
28 - qcom,msm8953-mdp5
29 - qcom,msm8974-mdp5
30 - qcom,msm8976-mdp5
31 - qcom,msm8994-mdp5
32 - qcom,msm8996-mdp5
33 - qcom,sdm630-mdp5
34 - qcom,sdm660-mdp5
35 - const: qcom,mdp5
38 pattern: '^display-controller@[0-9a-f]+$'
43 reg-names:
45 - const: mdp_phys
54 clock-names:
56 - minItems: 4
58 - const: iface
59 - const: bus
60 - const: core
61 - const: vsync
62 - const: lut
63 - const: tbu
64 - const: tbu_rt
66 - items:
67 - const: iface
68 - const: bus
69 - const: core
70 - const: iommu
71 - const: vsync
76 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
77 - description: Interconnect path from mdp1 port to the data bus
78 - description: Interconnect path from rotator port to the data bus
80 interconnect-names:
83 - const: mdp0-mem
84 - const: mdp1-mem
85 - const: rotator-mem
89 - description: apps SMMU with the Stream-ID mask for Hard-Fail port0
91 power-domains:
94 operating-points-v2: true
95 opp-table:
107 "^port@[0-3]+$":
112 - port@0
115 - compatible
116 - reg
117 - reg-names
118 - clocks
119 - clock-names
120 - ports
125 - |
126 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
127 #include <dt-bindings/interrupt-controller/arm-gic.h>
128 display-controller@1a01000 {
131 reg-names = "mdp_phys";
133 interrupt-parent = <&mdss>;
136 clocks = <&gcc GCC_MDSS_AHB_CLK>,
137 <&gcc GCC_MDSS_AXI_CLK>,
138 <&gcc GCC_MDSS_MDP_CLK>,
139 <&gcc GCC_MDSS_VSYNC_CLK>;
140 clock-names = "iface",
146 #address-cells = <1>;
147 #size-cells = <0>;
152 remote-endpoint = <&dsi0_in>;