Lines Matching +full:gcc +full:- +full:apq8084

6 controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
10 - compatible:
11   * "qcom,mdp5" - MDP5
12 - reg: Physical base address and length of the controller's registers.
13 - reg-names: The names of register regions. The following regions are required:
15 - interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
16 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
17 - clock-names: the following clocks are required.
18 -   * "bus"
19 -   * "iface"
20 -   * "core"
21 -   * "vsync"
22 - ports: contains the list of output ports from MDP. These connect to interfaces
30 	Documentation/devicetree/bindings/media/video-interfaces.txt
34   For MSM8974 and APQ8084:
35 	 Port 0 -> MDP_INTF0 (eDP)
36 	 Port 1 -> MDP_INTF1 (DSI1)
37 	 Port 2 -> MDP_INTF2 (DSI2)
38 	 Port 3 -> MDP_INTF3 (HDMI)
41 	 Port 0 -> MDP_INTF1 (DSI1)
44 	 Port 0 -> MDP_INTF1 (DSI1)
45 	 Port 1 -> MDP_INTF2 (DSI2)
46 	 Port 2 -> MDP_INTF3 (HDMI)
49 - clock-names: the following clocks are optional:
63 		reg-names = "mdss_phys", "vbif_phys";
65 		power-domains = <&gcc MDSS_GDSC>;
67 		clocks = <&gcc GCC_MDSS_AHB_CLK>,
68 			 <&gcc GCC_MDSS_AXI_CLK>,
69 			 <&gcc GCC_MDSS_VSYNC_CLK>;
70 		clock-names = "iface",
76 		interrupt-controller;
77 		#interrupt-cells = <1>;
79 		#address-cells = <1>;
80 		#size-cells = <1>;
86 			reg-names = "mdp_phys";
88 			interrupt-parent = <&mdss>;
91 			clocks = <&gcc GCC_MDSS_AHB_CLK>,
92 				 <&gcc GCC_MDSS_AXI_CLK>,
93 				 <&gcc GCC_MDSS_MDP_CLK>,
94 				 <&gcc GCC_MDSS_VSYNC_CLK>;
95 			clock-names = "iface",
101 				#address-cells = <1>;
102 				#size-cells = <0>;
107 						remote-endpoint = <&dsi0_in>;
120 						remote-endpoint = <&mdp5_intf1_out>;
128 		dsi_phy0: dsi-phy@1a98300 {