Lines Matching +full:pll +full:- +full:master
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
28 - vdd-supply: phandle to vdd regulator device node
29 - vddio-supply: phandle to vdd-io regulator device node
30 - vdda-supply: phandle to vdda regulator device node
31 - phys: phandle to DSI PHY device node
32 - phy-names: the name of the corresponding PHY device
33 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34 - ports: Contains 2 DSI controller ports as child nodes. Each port contains
38 - panel@0: Node of panel connected to this DSI controller.
40 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
42 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43 the master link of the 2-DSI panel.
44 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45 driving a 2-DSI panel whose 2 links need receive command simultaneously.
46 - pinctrl-names: the pin control state names; should contain "default"
47 - pinctrl-0: the default pinctrl state (active)
48 - pinctrl-n: the "sleep" pinctrl state
49 - ports: contains DSI controller input and output ports as children, each
53 - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
57 - data-lanes: this describes how the physical DSI data lanes are mapped
62 [3] for more info on the data-lanes property.
66 data-lanes = <3 0 1 2>;
84 - compatible: Could be the following
85 * "qcom,dsi-phy-28nm-hpm"
86 * "qcom,dsi-phy-28nm-lp"
87 * "qcom,dsi-phy-20nm"
88 * "qcom,dsi-phy-28nm-8960"
89 * "qcom,dsi-phy-14nm"
90 * "qcom,dsi-phy-14nm-660"
91 * "qcom,dsi-phy-10nm"
92 * "qcom,dsi-phy-10nm-8998"
93 * "qcom,dsi-phy-7nm"
94 * "qcom,dsi-phy-7nm-8150"
95 - reg: Physical base address and length of the registers of PLL, PHY. Some
98 - reg-names: The names of register regions. The following regions are required:
107 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
109 - power-domains: Should be <&mmcc MDSS_GDSC>.
110 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
111 - clock-names: the following clocks are required:
115 - vddio-supply: phandle to vdd-io regulator device node
117 - vddio-supply: phandle to vdd-io regulator device node
118 - vcca-supply: phandle to vcca regulator device node
120 - vcca-supply: phandle to vcca regulator device node
122 - vdds-supply: phandle to vdds regulator device node
125 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
127 - qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
142 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
144 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
149 compatible = "qcom,mdss-dsi-ctrl";
150 qcom,dsi-host-index = <0>;
151 interrupt-parent = <&mdp>;
153 reg-names = "dsi_ctrl";
155 power-domains = <&mmcc MDSS_GDSC>;
156 clock-names =
173 assigned-clocks =
176 assigned-clock-parents =
180 vdda-supply = <&pma8084_l2>;
181 vdd-supply = <&pma8084_l22>;
182 vddio-supply = <&pma8084_l12>;
185 phy-names ="dsi-phy";
187 qcom,dual-dsi-mode;
188 qcom,master-dsi;
189 qcom,sync-dual-dsi;
191 qcom,mdss-mdp-transfer-time-us = <12000>;
193 pinctrl-names = "default", "sleep";
194 pinctrl-0 = <&dsi_active>;
195 pinctrl-1 = <&dsi_suspend>;
198 #address-cells = <1>;
199 #size-cells = <0>;
204 remote-endpoint = <&mdp_intf1_out>;
211 remote-endpoint = <&panel_in>;
212 data-lanes = <0 1 2 3>;
222 power-supply = <...>;
227 remote-endpoint = <&dsi0_out>;
233 dsi_phy0: dsi-phy@fd922a00 {
234 compatible = "qcom,dsi-phy-28nm-hpm";
235 qcom,dsi-phy-index = <0>;
236 reg-names =
243 clock-names = "iface";
245 #clock-cells = <1>;
246 vddio-supply = <&pma8084_l12>;
248 qcom,dsi-phy-regulator-ldo-mode;