Lines Matching +full:pll +full:- +full:master
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8996-dsi-ctrl
23 - qcom,msm8998-dsi-ctrl
24 - qcom,qcm2290-dsi-ctrl
25 - qcom,sc7180-dsi-ctrl
26 - qcom,sc7280-dsi-ctrl
27 - qcom,sdm660-dsi-ctrl
28 - qcom,sdm670-dsi-ctrl
29 - qcom,sdm845-dsi-ctrl
30 - qcom,sm6115-dsi-ctrl
31 - qcom,sm6125-dsi-ctrl
32 - qcom,sm6350-dsi-ctrl
33 - qcom,sm6375-dsi-ctrl
34 - qcom,sm8150-dsi-ctrl
35 - qcom,sm8250-dsi-ctrl
36 - qcom,sm8350-dsi-ctrl
37 - qcom,sm8450-dsi-ctrl
38 - qcom,sm8550-dsi-ctrl
39 - qcom,sm8650-dsi-ctrl
40 - const: qcom,mdss-dsi-ctrl
41 - enum:
42 - qcom,dsi-ctrl-6g-qcm2290
43 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
49 reg-names:
58 - bus:: Display AHB clock.
59 - byte:: Display byte clock.
60 - byte_intf:: Display byte interface clock.
61 - core:: Display core clock.
62 - core_mss:: Core MultiMedia SubSystem clock.
63 - iface:: Display AXI clock.
64 - mdp_core:: MDP Core clock.
65 - mnoc:: MNOC clock
66 - pixel:: Display pixel clock.
70 clock-names:
77 phy-names:
81 syscon-sfpb:
85 qcom,dual-dsi-mode:
91 qcom,master-dsi:
94 Indicates if the DSI controller is the master DSI controller when
95 qcom,dual-dsi-mode enabled.
97 qcom,sync-dual-dsi:
101 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
103 assigned-clocks:
111 assigned-clock-parents:
115 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
117 power-domains:
120 operating-points-v2: true
122 opp-table:
133 $ref: /schemas/graph.yaml#/$defs/port-base
139 $ref: /schemas/media/video-interfaces.yaml#
142 data-lanes:
149 $ref: /schemas/graph.yaml#/$defs/port-base
155 $ref: /schemas/media/video-interfaces.yaml#
158 data-lanes:
165 - port@0
166 - port@1
168 avdd-supply:
172 refgen-supply:
176 vcca-supply:
180 vdd-supply:
184 vddio-supply:
186 VDD-IO regulator
188 vdda-supply:
193 - compatible
194 - reg
195 - reg-names
196 - interrupts
197 - clocks
198 - clock-names
199 - phys
200 - assigned-clocks
201 - assigned-clock-parents
202 - ports
205 - $ref: ../dsi-controller.yaml#
206 - if:
211 - qcom,apq8064-dsi-ctrl
216 clock-names:
218 - const: iface
219 - const: bus
220 - const: core_mmss
221 - const: src
222 - const: byte
223 - const: pixel
224 - const: core
226 - if:
231 - qcom,msm8916-dsi-ctrl
236 clock-names:
238 - const: mdp_core
239 - const: iface
240 - const: bus
241 - const: byte
242 - const: pixel
243 - const: core
245 - if:
250 - qcom,msm8953-dsi-ctrl
255 clock-names:
257 - const: mdp_core
258 - const: iface
259 - const: bus
260 - const: byte
261 - const: pixel
262 - const: core
264 - if:
269 - qcom,msm8226-dsi-ctrl
270 - qcom,msm8974-dsi-ctrl
275 clock-names:
277 - const: mdp_core
278 - const: iface
279 - const: bus
280 - const: byte
281 - const: pixel
282 - const: core
283 - const: core_mmss
285 - if:
290 - qcom,msm8996-dsi-ctrl
295 clock-names:
297 - const: mdp_core
298 - const: byte
299 - const: iface
300 - const: bus
301 - const: core_mmss
302 - const: pixel
303 - const: core
305 - if:
310 - qcom,msm8998-dsi-ctrl
311 - qcom,sm6125-dsi-ctrl
312 - qcom,sm6350-dsi-ctrl
317 clock-names:
319 - const: byte
320 - const: byte_intf
321 - const: pixel
322 - const: core
323 - const: iface
324 - const: bus
326 - if:
331 - qcom,sc7180-dsi-ctrl
332 - qcom,sc7280-dsi-ctrl
333 - qcom,sm8150-dsi-ctrl
334 - qcom,sm8250-dsi-ctrl
335 - qcom,sm8350-dsi-ctrl
336 - qcom,sm8450-dsi-ctrl
337 - qcom,sm8550-dsi-ctrl
338 - qcom,sm8650-dsi-ctrl
343 clock-names:
345 - const: byte
346 - const: byte_intf
347 - const: pixel
348 - const: core
349 - const: iface
350 - const: bus
352 - if:
357 - qcom,sdm660-dsi-ctrl
362 clock-names:
364 - const: mdp_core
365 - const: byte
366 - const: byte_intf
367 - const: mnoc
368 - const: iface
369 - const: bus
370 - const: core_mmss
371 - const: pixel
372 - const: core
374 - if:
379 - qcom,sdm845-dsi-ctrl
380 - qcom,sm6115-dsi-ctrl
381 - qcom,sm6375-dsi-ctrl
386 clock-names:
388 - const: byte
389 - const: byte_intf
390 - const: pixel
391 - const: core
392 - const: iface
393 - const: bus
398 - |
399 #include <dt-bindings/interrupt-controller/arm-gic.h>
400 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
401 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
402 #include <dt-bindings/power/qcom-rpmpd.h>
405 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
407 reg-names = "dsi_ctrl";
409 #address-cells = <1>;
410 #size-cells = <0>;
412 interrupt-parent = <&mdss>;
421 clock-names = "byte",
429 phy-names = "dsi";
431 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
432 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
434 power-domains = <&rpmhpd SC7180_CX>;
435 operating-points-v2 = <&dsi_opp_table>;
438 #address-cells = <1>;
439 #size-cells = <0>;
444 remote-endpoint = <&dpu_intf1_out>;
451 remote-endpoint = <&sn65dsi86_in>;
452 data-lanes = <0 1 2 3>;