Lines Matching +full:dispcc +full:- +full:sc8280xp
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp
28 - qcom,sm8350-dp
29 - qcom,sm8650-dp
30 - items:
31 - enum:
32 - qcom,sm8150-dp
33 - qcom,sm8250-dp
34 - qcom,sm8450-dp
35 - qcom,sm8550-dp
36 - const: qcom,sm8350-dp
41 - description: ahb register block
42 - description: aux register block
43 - description: link register block
44 - description: p0 register block
45 - description: p1 register block
52 - description: AHB clock to enable register access
53 - description: Display Port AUX clock
54 - description: Display Port Link clock
55 - description: Link interface clock between DP and PHY
56 - description: Display Port Pixel clock
58 clock-names:
60 - const: core_iface
61 - const: core_aux
62 - const: ctrl_link
63 - const: ctrl_link_iface
64 - const: stream_pixel
66 assigned-clocks:
68 - description: link clock source
69 - description: pixel clock source
71 assigned-clock-parents:
73 - description: phy 0 parent
74 - description: phy 1 parent
79 phy-names:
81 - const: dp
83 operating-points-v2: true
85 opp-table:
88 power-domains:
91 aux-bus:
92 $ref: /schemas/display/dp-aux-bus.yaml#
94 data-lanes:
95 $ref: /schemas/types.yaml#/definitions/uint32-array
102 "#sound-dai-cells":
105 vdda-0p9-supply:
107 vdda-1p2-supply:
118 $ref: /schemas/graph.yaml#/$defs/port-base
123 $ref: /schemas/media/video-interfaces.yaml#
126 data-lanes:
132 link-frequencies:
139 - port@0
140 - port@1
143 - compatible
144 - reg
145 - interrupts
146 - clocks
147 - clock-names
148 - phys
149 - phy-names
150 - power-domains
151 - ports
157 - if:
162 - qcom,sc7280-edp
163 - qcom,sc8180x-edp
164 - qcom,sc8280xp-edp
167 "#sound-dai-cells": false
170 aux-bus: false
174 - "#sound-dai-cells"
179 - |
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
181 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
182 #include <dt-bindings/power/qcom-rpmpd.h>
184 displayport-controller@ae90000 {
185 compatible = "qcom,sc7180-dp";
191 interrupt-parent = <&mdss>;
193 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
194 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
198 clock-names = "core_iface", "core_aux",
202 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
203 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
205 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
208 phy-names = "dp";
210 #sound-dai-cells = <0>;
212 power-domains = <&rpmhpd SC7180_CX>;
215 #address-cells = <1>;
216 #size-cells = <0>;
221 remote-endpoint = <&dpu_intf0_out>;
228 remote-endpoint = <&typec>;
229 data-lanes = <0 1>;
230 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;