Lines Matching +full:merge +full:- +full:mute
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display merge
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
16 MERGE device node must be siblings to the central MMSYS_CONFIG node.
24 - enum:
25 - mediatek,mt8173-disp-merge
26 - mediatek,mt8195-disp-merge
27 - mediatek,mt8195-mdp3-merge
28 - items:
29 - const: mediatek,mt6795-disp-merge
30 - const: mediatek,mt8173-disp-merge
31 - items:
32 - const: mediatek,mt8188-disp-merge
33 - const: mediatek,mt8195-disp-merge
41 power-domains:
44 Documentation/devicetree/bindings/power/power-domain.yaml for details.
50 clock-names:
52 - items:
53 - const: merge
54 - items:
55 - const: merge
56 - const: merge_async
58 mediatek,merge-fifo-en:
60 The setting of merge fifo is mainly provided for the display latency
61 buffer to ensure that the back-end panel display data will not be
63 According to the merge fifo settings, when the water level is detected
68 mediatek,merge-mute:
69 description: Support mute function. Mute the content of merge output.
72 mediatek,gce-client-reg:
76 defined in the header include/dt-bindings/gce/<chip>-gce.h.
77 $ref: /schemas/types.yaml#/definitions/phandle-array
86 - compatible
87 - reg
88 - power-domains
89 - clocks
94 - |
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 #include <dt-bindings/clock/mt8173-clk.h>
97 #include <dt-bindings/power/mt8173-power.h>
100 #address-cells = <2>;
101 #size-cells = <2>;
103 merge@14017000 {
104 compatible = "mediatek,mt8173-disp-merge";
106 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
108 clock-names = "merge";