Lines Matching +full:hdr +full:- +full:engine
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
15 designed for HDR video and graphics conversion in the external display path.
16 It handles multiple HDR input types and performs tone mapping, color
18 output the required HDR or SDR signal to the subsequent display path.
19 This engine is composed of two video frontends, two graphic frontends,
21 These two function blocks read the pre-programmed registers from DRAM and
22 set them to HW in the v-blanking period.
27 - const: mediatek,mt8195-disp-ethdr
28 - items:
29 - const: mediatek,mt8188-disp-ethdr
30 - const: mediatek,mt8195-disp-ethdr
35 reg-names:
37 - const: mixer
38 - const: vdo_fe0
39 - const: vdo_fe1
40 - const: gfx_fe0
41 - const: gfx_fe1
42 - const: vdo_be
43 - const: adl_ds
54 - description: mixer clock
55 - description: video frontend 0 clock
56 - description: video frontend 1 clock
57 - description: graphic frontend 0 clock
58 - description: graphic frontend 1 clock
59 - description: video backend clock
60 - description: autodownload and menuload clock
61 - description: video frontend 0 async clock
62 - description: video frontend 1 async clock
63 - description: graphic frontend 0 async clock
64 - description: graphic frontend 1 async clock
65 - description: video backend async clock
66 - description: ethdr top clock
68 clock-names:
70 - const: mixer
71 - const: vdo_fe0
72 - const: vdo_fe1
73 - const: gfx_fe0
74 - const: gfx_fe1
75 - const: vdo_be
76 - const: adl_ds
77 - const: vdo_fe0_async
78 - const: vdo_fe1_async
79 - const: gfx_fe0_async
80 - const: gfx_fe1_async
81 - const: vdo_be_async
82 - const: ethdr_top
84 power-domains:
89 - description: video frontend 0 async reset
90 - description: video frontend 1 async reset
91 - description: graphic frontend 0 async reset
92 - description: graphic frontend 1 async reset
93 - description: video backend async reset
95 reset-names:
97 - const: vdo_fe0_async
98 - const: vdo_fe1_async
99 - const: gfx_fe0_async
100 - const: gfx_fe1_async
101 - const: vdo_be_async
103 mediatek,gce-client-reg:
104 $ref: /schemas/types.yaml#/definitions/phandle-array
110 include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
114 - compatible
115 - reg
116 - clocks
117 - clock-names
118 - interrupts
119 - power-domains
120 - resets
121 - mediatek,gce-client-reg
126 - |
127 #include <dt-bindings/interrupt-controller/arm-gic.h>
128 #include <dt-bindings/clock/mt8195-clk.h>
129 #include <dt-bindings/gce/mt8195-gce.h>
130 #include <dt-bindings/memory/mt8195-memory-port.h>
131 #include <dt-bindings/power/mt8195-power.h>
132 #include <dt-bindings/reset/mt8195-resets.h>
135 #address-cells = <2>;
136 #size-cells = <2>;
138 hdr-engine@1c114000 {
139 compatible = "mediatek,mt8195-disp-ethdr";
147 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
149 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
169 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
173 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
182 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",