Lines Matching +full:reset +full:- +full:synchronized
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 - $ref: /schemas/display/dsi-controller.yaml#
25 - enum:
26 - mediatek,mt2701-dsi
27 - mediatek,mt7623-dsi
28 - mediatek,mt8167-dsi
29 - mediatek,mt8173-dsi
30 - mediatek,mt8183-dsi
31 - mediatek,mt8186-dsi
32 - mediatek,mt8188-dsi
33 - items:
34 - enum:
35 - mediatek,mt6795-dsi
36 - const: mediatek,mt8173-dsi
37 - items:
38 - enum:
39 - mediatek,mt8195-dsi
40 - const: mediatek,mt8183-dsi
48 power-domains:
53 - description: Engine Clock
54 - description: Digital Clock
55 - description: HS Clock
57 clock-names:
59 - const: engine
60 - const: digital
61 - const: hs
69 phy-names:
71 - const: dphy
77 port of an attached DSI panel or DSI-to-eDP encoder chip.
80 - compatible
81 - reg
82 - interrupts
83 - power-domains
84 - clocks
85 - clock-names
86 - phys
87 - phy-names
88 - port
93 - |
94 #include <dt-bindings/clock/mt8183-clk.h>
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 #include <dt-bindings/interrupt-controller/irq.h>
97 #include <dt-bindings/power/mt8183-power.h>
98 #include <dt-bindings/phy/phy.h>
99 #include <dt-bindings/reset/mt8183-resets.h>
102 #address-cells = <2>;
103 #size-cells = <2>;
106 compatible = "mediatek,mt8183-dsi";
109 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
113 clock-names = "engine", "digital", "hs";
116 phy-names = "dphy";
119 remote-endpoint = <&panel_in>;