Lines Matching +full:digital +full:- +full:output

5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
6 channel output.
9 - compatible: "mediatek,<chip>-dsi"
10 - the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14   See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "engine", "digital", and "hs"
16 - phys: phandle link to the MIPI D-PHY controller.
17 - phy-names: must contain "dphy"
18 - port: Output port node with endpoint definitions as described in
20   to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
23 - resets: list of phandle + reset specifier pair, as described in [1].
30 See phy/mediatek,dsi-phy.yaml
34 mipi_tx0: mipi-dphy@10215000 {
35 	compatible = "mediatek,mt8173-mipi-tx";
38 	clock-output-names = "mipi_tx0_pll";
39 	#clock-cells = <0>;
40 	#phy-cells = <0>;
41 	drive-strength-microamp = <4600>;
42 	nvmem-cells= <&mipi_tx_calibration>;
43 	nvmem-cell-names = "calibration-data";
47 	compatible = "mediatek,mt8173-dsi";
52 	clock-names = "engine", "digital", "hs";
55 	phy-names = "dphy";
59 			remote-endpoint = <&panel_in>;