Lines Matching +full:master +full:- +full:dsi
25 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
39 "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
40 "mediatek,<chip>-disp-postmask" - control round corner for display frame
41 "mediatek,<chip>-disp-split" - split stream to two encoders
42 "mediatek,<chip>-disp-ufoe" - data compression engine
43 "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
44 "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
45 "mediatek,<chip>-disp-mutex" - display mutex
46 "mediatek,<chip>-disp-od" - overdrive
48 - reg: Physical base address and length of the function block register space
49 - interrupts: The interrupt signal from the function block (required, except for
51 - clocks: device clocks
52 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
53 For most function blocks this is just a single clock input. Only the DSI and
55 mediatek,dsi.txt and mediatek,dpi.txt, respectively.
59 - compatible: Should be one of
60 "mediatek,<chip>-disp-ovl"
61 "mediatek,<chip>-disp-rdma"
62 "mediatek,<chip>-disp-wdma"
64 - larb: Should contain a phandle pointing to the local arbiter device as defined
65 in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
66 - iommus: Should point to the respective IOMMU block with master port as
71 - mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
74 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
75 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
76 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
80 mmsys: clock-controller@14000000 {
81 compatible = "mediatek,mt8173-mmsys", "syscon";
83 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
84 #clock-cells = <1>;
88 compatible = "mediatek,mt8173-disp-ovl";
91 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
98 compatible = "mediatek,mt8173-disp-ovl";
101 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
108 compatible = "mediatek,mt8173-disp-rdma";
111 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
115 mediatek,rdma-fifosize = <8192>;
119 compatible = "mediatek,mt8173-disp-rdma";
122 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
129 compatible = "mediatek,mt8173-disp-rdma";
132 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
139 compatible = "mediatek,mt8173-disp-wdma";
142 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
149 compatible = "mediatek,mt8173-disp-wdma";
152 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
159 compatible = "mediatek,mt8173-disp-color";
162 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
167 compatible = "mediatek,mt8173-disp-color";
170 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
175 compatible = "mediatek,mt8173-disp-aal";
178 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
183 compatible = "mediatek,mt8173-disp-gamma";
186 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
191 compatible = "mediatek,mt8173-disp-ufoe";
194 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
198 dsi0: dsi@1401b000 {
199 /* See mediatek,dsi.txt for details */
207 compatible = "mediatek,mt8173-disp-mutex";
210 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
215 compatible = "mediatek,mt8173-disp-od";
217 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;