Lines Matching +full:imx8mq +full:- +full:clock
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: iMX8MQ Display Controller Subsystem (DCSS)
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
33 - description: DTG interrupt used to signal context loader trigger time
34 - description: DTG interrupt for Vblank
36 interrupt-names:
38 - const: ctxld
39 - const: ctxld_kick
40 - const: vblank
44 - description: Display APB clock for all peripheral PIO access interfaces
45 - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
46 - description: RTRAM clock
47 - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
48 - description: DTRC clock, needed by video decompressor
50 clock-names:
52 - const: apb
53 - const: axi
54 - const: rtrm
55 - const: pix
56 - const: dtrc
58 assigned-clocks:
60 - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
61 - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
62 - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
65 assigned-clock-parents:
67 - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
68 - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
69 - description: Phandle and clock specifier of IMX8MQ_CLK_27M
71 assigned-clock-rates:
73 - description: Must be 800 MHz
74 - description: Must be 400 MHz
84 - |
85 #include <dt-bindings/clock/imx8mq-clock.h>
86 dcss: display-controller@32e00000 {
87 compatible = "nxp,imx8mq-dcss";
90 interrupt-names = "ctxld", "ctxld_kick", "vblank";
91 interrupt-parent = <&irqsteer>;
95 clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
96 assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
98 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
100 assigned-clock-rates = <800000000>,
104 remote-endpoint = <&hdmi_in>;