Lines Matching +full:display +full:- +full:bridge
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
19 display controllers.
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
33 u8 value representing the display controller index that the pixel link
36 fsl,dc-stream-id:
39 u8 value representing the display controller stream index that the pixel
52 "^port@[1-4]$":
54 description: The pixel link output port node to downstream bridge.
57 - port@0
58 - port@1
59 - port@2
60 - port@3
61 - port@4
64 - if:
68 const: fsl,imx8qxp-dc-pixel-link
71 fsl,dc-id:
74 - if:
78 const: fsl,imx8qm-dc-pixel-link
81 fsl,dc-id:
85 - compatible
86 - fsl,dc-id
87 - fsl,dc-stream-id
88 - ports
93 - |
94 dc0-pixel-link0 {
95 compatible = "fsl,imx8qxp-dc-pixel-link";
96 fsl,dc-id = /bits/ 8 <0>;
97 fsl,dc-stream-id = /bits/ 8 <0>;
100 #address-cells = <1>;
101 #size-cells = <0>;
108 remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
114 #address-cells = <1>;
115 #size-cells = <0>;
120 remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
125 remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;