Lines Matching +full:bus +full:- +full:dmc
1 * Rockchip rk3399 DMC (Dynamic Memory Controller) device
4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
15 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
19 - interrupts: The CPU interrupt number. The interrupt specifier
23 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
28 - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
29 it selects the DDR3 cl-trp-trcd type. It must be
34 - rockchip,pd_idle : Configure the PD_IDLE value. Defines the
35 power-down idle period in which memories are
36 placed into power-down mode if bus is idle
39 - rockchip,sr_idle : Configure the SR_IDLE value. Defines the
40 self-refresh idle period in which memories are
41 placed into self-refresh mode if bus is idle
46 - rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
48 into self-refresh mode and memory controller
49 clock arg gating started if bus is idle for
52 - rockchip,srpd_lite_idle : Defines the self-refresh power down idle
54 self-refresh power down mode if bus is idle
58 - rockchip,standby_idle : Defines the standby idle period in which
59 memories are placed into self-refresh mode.
61 be gated if bus is idle for standby_idle * DFI
64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
69 - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
74 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
80 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
84 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
88 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
93 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
97 - rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
100 - rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
106 - rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
110 - rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
114 - rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
119 - rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
123 - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
126 - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
132 - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
136 - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
140 - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
144 - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
148 - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
152 - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
156 - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
161 compatible = "operating-points-v2";
164 opp-hz = /bits/ 64 <300000000>;
165 opp-microvolt = <900000>;
168 opp-hz = /bits/ 64 <666000000>;
169 opp-microvolt = <900000>;
173 dmc: dmc {
174 compatible = "rockchip,rk3399-dmc";
175 devfreq-events = <&dfi>;
178 clock-names = "dmc_clk";
179 operating-points-v2 = <&dmc_opp_table>;
180 center-supply = <&ppvar_centerlogic>;