Lines Matching +full:opp +full:- +full:134000000
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
31 SoC has different sub-blocks. Therefore, such difference should be specified
36 - compatible: Should be "samsung,exynos-bus".
37 - clock-names : the name of clock used by the bus, "bus".
38 - clocks : phandles for clock specified in "clock-names" property.
39 - operating-points-v2: the OPP table including frequency/voltage information
43 - vdd-supply: the regulator to provide the buses with the voltage.
44 - devfreq-events: the devfreq-event device to monitor the current utilization
48 - devfreq: the parent bus device.
51 - exynos,saturation-ratio: the percentage value which is used to calibrate
56 - #interconnect-cells: should be 0.
57 - interconnects: as documented in ../interconnect.txt, describes a path at the
64 - samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data
67 Detailed correlation between sub-blocks and power line according to Exynos SoC:
68 - In case of Exynos3250, there are two power line as following:
69 VDD_MIF |--- DMC
71 VDD_INT |--- LEFTBUS (parent device)
72 |--- PERIL
73 |--- MFC
74 |--- G3D
75 |--- RIGHTBUS
76 |--- PERIR
77 |--- FSYS
78 |--- LCD0
79 |--- PERIR
80 |--- ISP
81 |--- CAM
83 - In case of Exynos4210, there is one power line as following:
84 VDD_INT |--- DMC (parent device)
85 |--- LEFTBUS
86 |--- PERIL
87 |--- MFC(L)
88 |--- G3D
89 |--- TV
90 |--- LCD0
91 |--- RIGHTBUS
92 |--- PERIR
93 |--- MFC(R)
94 |--- CAM
95 |--- FSYS
96 |--- GPS
97 |--- LCD0
98 |--- LCD1
100 - In case of Exynos4x12, there are two power line as following:
101 VDD_MIF |--- DMC
103 VDD_INT |--- LEFTBUS (parent device)
104 |--- PERIL
105 |--- MFC(L)
106 |--- G3D
107 |--- TV
108 |--- IMAGE
109 |--- RIGHTBUS
110 |--- PERIR
111 |--- MFC(R)
112 |--- CAM
113 |--- FSYS
114 |--- GPS
115 |--- LCD0
116 |--- ISP
118 - In case of Exynos5422, there are two power line as following:
119 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
120 |--- DREX 1
122 VDD_INT |--- NoC_Core (parent device)
123 |--- G2D
124 |--- G3D
125 |--- DISP1
126 |--- NoC_WCORE
127 |--- GSCL
128 |--- MSCL
129 |--- ISP
130 |--- MFC
131 |--- GEN
132 |--- PERIS
133 |--- PERIC
134 |--- FSYS
135 |--- FSYS2
137 - In case of Exynos5433, there is VDD_INT power line as following:
138 VDD_INT |--- G2D (parent device)
139 |--- MSCL
140 |--- GSCL
141 |--- JPEG
142 |--- MFC
143 |--- HEVC
144 |--- BUS0
145 |--- BUS1
146 |--- BUS2
147 |--- PERIS (Fixed clock rate)
148 |--- PERIC (Fixed clock rate)
149 |--- FSYS (Fixed clock rate)
156 - MIF (Memory Interface) block
157 : VDD_MIF |--- DMC (Dynamic Memory Controller)
159 - INT (Internal) block
160 : VDD_INT |--- LEFTBUS (parent device)
161 |--- PERIL
162 |--- MFC
163 |--- G3D
164 |--- RIGHTBUS
165 |--- FSYS
166 |--- LCD0
167 |--- PERIR
168 |--- ISP
169 |--- CAM
171 - MIF bus's frequency/voltage table
172 -----------------------
174 -----------------------
180 -----------------------
182 - INT bus's frequency/voltage table
183 ----------------------------------------------------------
188 ----------------------------------------------------------
190 ----------------------------------------------------------
192 ----------------------------------------------------------
198 ----------------------------------------------------------
205 compatible = "samsung,exynos-bus";
207 clock-names = "bus";
208 operating-points-v2 = <&bus_dmc_opp_table>;
213 compatible = "operating-points-v2";
214 opp-shared;
216 opp-50000000 {
217 opp-hz = /bits/ 64 <50000000>;
218 opp-microvolt = <800000>;
220 opp-100000000 {
221 opp-hz = /bits/ 64 <100000000>;
222 opp-microvolt = <800000>;
224 opp-134000000 {
225 opp-hz = /bits/ 64 <134000000>;
226 opp-microvolt = <800000>;
228 opp-200000000 {
229 opp-hz = /bits/ 64 <200000000>;
230 opp-microvolt = <825000>;
232 opp-400000000 {
233 opp-hz = /bits/ 64 <400000000>;
234 opp-microvolt = <875000>;
239 compatible = "samsung,exynos-bus";
241 clock-names = "bus";
242 operating-points-v2 = <&bus_leftbus_opp_table>;
247 compatible = "samsung,exynos-bus";
249 clock-names = "bus";
250 operating-points-v2 = <&bus_leftbus_opp_table>;
255 compatible = "samsung,exynos-bus";
257 clock-names = "bus";
258 operating-points-v2 = <&bus_leftbus_opp_table>;
263 compatible = "samsung,exynos-bus";
265 clock-names = "bus";
266 operating-points-v2 = <&bus_leftbus_opp_table>;
271 compatible = "samsung,exynos-bus";
273 clock-names = "bus";
274 operating-points-v2 = <&bus_mcuisp_opp_table>;
279 compatible = "samsung,exynos-bus";
281 clock-names = "bus";
282 operating-points-v2 = <&bus_isp_opp_table>;
287 compatible = "samsung,exynos-bus";
289 clock-names = "bus";
290 operating-points-v2 = <&bus_peril_opp_table>;
295 compatible = "samsung,exynos-bus";
297 clock-names = "bus";
298 operating-points-v2 = <&bus_leftbus_opp_table>;
303 compatible = "operating-points-v2";
304 opp-shared;
306 opp-50000000 {
307 opp-hz = /bits/ 64 <50000000>;
308 opp-microvolt = <900000>;
310 opp-80000000 {
311 opp-hz = /bits/ 64 <80000000>;
312 opp-microvolt = <900000>;
314 opp-100000000 {
315 opp-hz = /bits/ 64 <100000000>;
316 opp-microvolt = <1000000>;
318 opp-134000000 {
319 opp-hz = /bits/ 64 <134000000>;
320 opp-microvolt = <1000000>;
322 opp-200000000 {
323 opp-hz = /bits/ 64 <200000000>;
324 opp-microvolt = <1000000>;
329 compatible = "operating-points-v2";
330 opp-shared;
332 opp-50000000 {
333 opp-hz = /bits/ 64 <50000000>;
335 opp-80000000 {
336 opp-hz = /bits/ 64 <80000000>;
338 opp-100000000 {
339 opp-hz = /bits/ 64 <100000000>;
341 opp-200000000 {
342 opp-hz = /bits/ 64 <200000000>;
344 opp-400000000 {
345 opp-hz = /bits/ 64 <400000000>;
350 compatible = "operating-points-v2";
351 opp-shared;
353 opp-50000000 {
354 opp-hz = /bits/ 64 <50000000>;
356 opp-80000000 {
357 opp-hz = /bits/ 64 <80000000>;
359 opp-100000000 {
360 opp-hz = /bits/ 64 <100000000>;
362 opp-200000000 {
363 opp-hz = /bits/ 64 <200000000>;
365 opp-300000000 {
366 opp-hz = /bits/ 64 <300000000>;
371 compatible = "operating-points-v2";
372 opp-shared;
374 opp-50000000 {
375 opp-hz = /bits/ 64 <50000000>;
377 opp-80000000 {
378 opp-hz = /bits/ 64 <80000000>;
380 opp-100000000 {
381 opp-hz = /bits/ 64 <100000000>;
387 in exynos3250-rinato.dts is listed below:
390 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
391 vdd-supply = <&buck1_reg>; /* VDD_MIF */
396 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
397 vdd-supply = <&buck3_reg>;
437 An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
442 compatible = "samsung,exynos-bus";
444 clock-names = "bus";
445 operating-points-v2 = <&bus_dmc_opp_table>;
446 samsung,data-clock-ratio = <4>;
447 #interconnect-cells = <0>;
451 compatible = "samsung,exynos-bus";
453 clock-names = "bus";
454 operating-points-v2 = <&bus_leftbus_opp_table>;
455 #interconnect-cells = <0>;
460 compatible = "samsung,exynos-bus";
462 clock-names = "bus";
463 operating-points-v2 = <&bus_display_opp_table>;
464 #interconnect-cells = <0>;
469 compatible = "operating-points-v2";
474 compatible = "operating-points-v2";
479 compatible = "operating-points-v2";
484 compatible = "samsung,exynos4212-mixer";