Lines Matching +full:rtic +full:- +full:a
3 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
6 -Overview
7 -SEC 4 Node
8 -Job Ring Node
9 -Run Time Integrity Check (RTIC) Node
10 -Run Time Integrity Check (RTIC) Memory Node
11 -Secure Non-Volatile Storage (SNVS) Node
12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
13 -Full Example
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
31 equal to the number of Descriptor Controller (DECO) engines in a particular
37 Each JR is located on a separate 4k page, they may (or may not) be made visible
38 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
50 (RTIC) function within the SEC 4 block.
54 - compatible
57 Definition: Must include "fsl,sec-v4.0"
59 - fsl,sec-era
62 Definition: A standard property. Define the 'ERA' of the SEC
65 - #address-cells
68 Definition: A standard property. Defines the number of cells
71 - #size-cells
74 Definition: A standard property. Defines the number of cells
78 - reg
80 Value type: <prop-encoded-array>
81 Definition: A standard property. Specifies the physical
85 - ranges
87 Value type: <prop-encoded-array>
88 Definition: A standard property. Specifies the physical address
89 range of the SEC 4.0 register space (-SNVS not included). A
93 - interrupts
95 Value type: <prop_encoded-array>
102 - clocks
104 Value type: <prop_encoded-array>
105 Definition: A list of phandle and clock specifier pairs describing
108 - clock-names
111 Definition: A list of clock name strings in the same order as the
123 compatible = "fsl,sec-v4.0";
124 fsl,sec-era = <2>;
125 #address-cells = <1>;
126 #size-cells = <1>;
129 interrupt-parent = <&mpic>;
135 clock-names = "mem", "aclk", "ipg", "emi_slow";
142 compatible = "fsl,sec-v4.0";
143 #address-cells = <1>;
144 #size-cells = <1>;
152 clock-names = "mem", "aclk", "ipg";
165 - compatible
168 Definition: Must include "fsl,sec-v4.0-job-ring"
170 - reg
172 Value type: <prop-encoded-array>
173 Definition: Specifies a two JR parameters: an offset from
176 - fsl,liodn
177 Usage: optional-but-recommended
178 Value type: <prop-encoded-array>
181 the ppid-to-liodn table that specifies the PPID to LIODN mapping.
182 Needed if the PAMU is used. Value is a 12 bit value
183 where value is a LIODN ID for this JR. This property is
186 - interrupts
188 Value type: <prop_encoded-array>
197 compatible = "fsl,sec-v4.0-job-ring";
200 interrupt-parent = <&mpic>;
206 Run Time Integrity Check (RTIC) Node
208 Child node of the crypto node. Defines a register space that
212 change. If any memory is modified, a Security Violation is
216 - compatible
219 Definition: Must include "fsl,sec-v4.0-rtic".
221 - #address-cells
224 Definition: A standard property. Defines the number of cells
226 have a value of 1.
228 - #size-cells
231 Definition: A standard property. Defines the number of cells
233 child nodes. Must have a value of 1.
235 - reg
237 Value type: <prop-encoded-array>
238 Definition: A standard property. Specifies a two parameters:
242 - ranges
244 Value type: <prop-encoded-array>
245 Definition: A standard property. Specifies the physical address
246 range of the SEC 4 register space (-SNVS not included). A
251 rtic@6000 {
252 compatible = "fsl,sec-v4.0-rtic";
253 #address-cells = <1>;
254 #size-cells = <1>;
260 Run Time Integrity Check (RTIC) Memory Node
261 A child node that defines individual RTIC memory regions that are used to
262 perform run-time integrity check of memory areas that should not modified.
263 The node defines a register that contains the memory address &
264 length (combined) and a second register that contains the hash result
267 - compatible
270 Definition: Must include "fsl,sec-v4.0-rtic-memory".
272 - reg
274 Value type: <prop-encoded-array>
275 Definition: A standard property. Specifies two parameters:
278 1. The location of the RTIC memory address & length registers.
279 2. The location RTIC hash result.
281 - fsl,rtic-region
282 Usage: optional-but-recommended
283 Value type: <prop-encoded-array>
287 the address is represented as a 64 bit quantity followed
288 by a 32 bit length.
290 - fsl,liodn
291 Usage: optional-but-recommended
292 Value type: <prop-encoded-array>
295 the ppid-to-liodn table that specifies the PPID to LIODN
296 mapping. Needed if the PAMU is used. Value is a 12 bit value
297 where value is a LIODN ID for this RTIC memory region. This
301 rtic-a@0 {
302 compatible = "fsl,sec-v4.0-rtic-memory";
305 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
309 Secure Non-Volatile Storage (SNVS) Node
317 - compatible
320 Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
322 - reg
324 Value type: <prop-encoded-array>
325 Definition: A standard property. Specifies the physical
329 - #address-cells
332 Definition: A standard property. Defines the number of cells
334 have a value of 1.
336 - #size-cells
339 Definition: A standard property. Defines the number of cells
341 child nodes. Must have a value of 1.
343 - ranges
345 Value type: <prop-encoded-array>
346 Definition: A standard property. Specifies the physical address
347 range of the SNVS register space. A triplet that includes
350 - interrupts
352 Value type: <prop_encoded-array>
361 compatible = "fsl,sec-v4.0-mon", "syscon";
364 interrupt-parent = <&mpic>;
369 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
371 A SNVS child node that defines SNVS LP RTC.
373 - compatible
376 Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
378 - interrupts
380 Value type: <prop_encoded-array>
387 - regmap
392 - offset
397 - clocks
400 Value type: <prop_encoded-array>
401 Definition: a clock specifier describing the clock required for
404 - clock-names
408 Definition: clock name string should be "snvs-rtc".
412 compatible = "fsl,sec-v4.0-mon-rtc-lp";
417 clock-names = "snvs-rtc";
423 The snvs-pwrkey is designed to enable POWER key function which controlled
427 - compatible:
430 Definition: Mush include "fsl,sec-v4.0-pwrkey".
432 - interrupts:
434 Value type: <prop_encoded-array>
437 - linux,keycode:
442 - wakeup-source:
445 Definition: Button can wake-up the system.
447 - regmap:
453 snvs-pwrkey@020cc000 {
454 compatible = "fsl,sec-v4.0-pwrkey";
458 wakeup-source;
465 compatible = "fsl,sec-v4.0";
466 #address-cells = <1>;
467 #size-cells = <1>;
470 interrupt-parent = <&mpic>;
474 compatible = "fsl,sec-v4.0-job-ring";
476 interrupt-parent = <&mpic>;
481 compatible = "fsl,sec-v4.0-job-ring";
483 interrupt-parent = <&mpic>;
488 compatible = "fsl,sec-v4.0-job-ring";
490 interrupt-parent = <&mpic>;
495 compatible = "fsl,sec-v4.0-job-ring";
497 interrupt-parent = <&mpic>;
501 rtic@6000 {
502 compatible = "fsl,sec-v4.0-rtic";
503 #address-cells = <1>;
504 #size-cells = <1>;
508 rtic_a: rtic-a@0 {
509 compatible = "fsl,sec-v4.0-rtic-memory";
513 rtic_b: rtic-b@20 {
514 compatible = "fsl,sec-v4.0-rtic-memory";
518 rtic_c: rtic-c@40 {
519 compatible = "fsl,sec-v4.0-rtic-memory";
523 rtic_d: rtic-d@60 {
524 compatible = "fsl,sec-v4.0-rtic-memory";
531 compatible = "fsl,sec-v4.0-mon";
536 compatible = "fsl,sec-v4.0-mon-rtc-lp";
541 clock-names = "snvs-rtc";
544 snvs-pwrkey@020cc000 {
545 compatible = "fsl,sec-v4.0-pwrkey";
549 wakeup-source;