Lines Matching +full:0 +full:- +full:rtic +full:- +full:memory
1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
40 - items:
41 - const: fsl,sec-v5.4
42 - const: fsl,sec-v5.0
43 - const: fsl,sec-v4.0
44 - items:
45 - enum:
46 - fsl,imx6ul-caam
47 - fsl,sec-v5.0
48 - const: fsl,sec-v4.0
49 - const: fsl,sec-v4.0
57 '#address-cells':
60 '#size-cells':
67 clock-names:
73 dma-coherent: true
78 fsl,sec-era:
83 '^jr@[0-9a-f]+$':
96 - items:
97 - const: fsl,sec-v5.4-job-ring
98 - const: fsl,sec-v5.0-job-ring
99 - const: fsl,sec-v4.0-job-ring
100 - items:
101 - const: fsl,sec-v5.0-job-ring
102 - const: fsl,sec-v4.0-job-ring
103 - const: fsl,sec-v4.0-job-ring
113 Specifies the LIODN to be used in conjunction with the ppid-to-liodn
118 maximum: 0xfff
120 '^rtic@[0-9a-f]+$':
124 Run Time Integrity Check (RTIC) Node. Defines a register space that
127 addresses are checked by HW to monitor any change. If any memory is
133 - items:
134 - const: fsl,sec-v5.4-rtic
135 - const: fsl,sec-v5.0-rtic
136 - const: fsl,sec-v4.0-rtic
137 - const: fsl,sec-v4.0-rtic
148 '#address-cells':
151 '#size-cells':
155 '^rtic-[a-z]@[0-9a-f]+$':
159 Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
160 memory regions that are used to perform run-time integrity check of
161 memory areas that should not modified. The node defines a register
162 that contains the memory address & length (combined) and a second
168 - items:
169 - const: fsl,sec-v5.4-rtic-memory
170 - const: fsl,sec-v5.0-rtic-memory
171 - const: fsl,sec-v4.0-rtic-memory
172 - const: fsl,sec-v4.0-rtic-memory
176 - description: RTIC memory address
177 - description: RTIC hash result
182 ppid-to-liodn table that specifies the PPID to LIODN mapping.
187 maximum: 0xfff
189 fsl,rtic-region:
195 $ref: /schemas/types.yaml#/definitions/uint32-array
198 - compatible
199 - reg
200 - ranges
205 - |
207 compatible = "fsl,sec-v4.0";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0x300000 0x10000>;
211 ranges = <0 0x300000 0x10000>;
215 compatible = "fsl,sec-v4.0-job-ring";
216 reg = <0x1000 0x1000>;
221 compatible = "fsl,sec-v4.0-job-ring";
222 reg = <0x2000 0x1000>;
227 compatible = "fsl,sec-v4.0-job-ring";
228 reg = <0x3000 0x1000>;
233 compatible = "fsl,sec-v4.0-job-ring";
234 reg = <0x4000 0x1000>;
238 rtic@6000 {
239 compatible = "fsl,sec-v4.0-rtic";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 reg = <0x6000 0x100>;
243 ranges = <0x0 0x6100 0xe00>;
245 rtic-a@0 {
246 compatible = "fsl,sec-v4.0-rtic-memory";
247 reg = <0x00 0x20>, <0x100 0x80>;
250 rtic-b@20 {
251 compatible = "fsl,sec-v4.0-rtic-memory";
252 reg = <0x20 0x20>, <0x200 0x80>;
255 rtic-c@40 {
256 compatible = "fsl,sec-v4.0-rtic-memory";
257 reg = <0x40 0x20>, <0x300 0x80>;
260 rtic-d@60 {
261 compatible = "fsl,sec-v4.0-rtic-memory";
262 reg = <0x60 0x20>, <0x500 0x80>;