Lines Matching +full:opp +full:- +full:v2
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
20 For old implementation efuses are parsed to select the correct opp table and
28 - qcom,apq8064
29 - qcom,apq8096
30 - qcom,ipq5332
31 - qcom,ipq6018
32 - qcom,ipq8064
33 - qcom,ipq8074
34 - qcom,ipq9574
35 - qcom,msm8909
36 - qcom,msm8939
37 - qcom,msm8960
38 - qcom,msm8974
39 - qcom,msm8996
40 - qcom,qcs404
42 - compatible
45 '^opp-table(-[a-z0-9]+)?$':
47 - if:
51 - operating-points-v2-krait-cpu
52 - operating-points-v2-kryo-cpu
54 $ref: /schemas/opp/opp-v2-kryo-cpu.yaml#
56 - if:
59 const: operating-points-v2-qcom-level
61 $ref: /schemas/opp/opp-v2-qcom-level.yaml#
66 - if:
71 - qcom,qcs404
79 '^cpu@[0-9a-f]+$':
83 power-domains:
86 power-domain-names:
88 - const: cpr
91 - power-domains
92 - power-domain-names
95 '^opp-table(-[a-z0-9]+)?$':
99 const: operating-points-v2-kryo-cpu
102 '^opp-?[0-9]+$':
104 - required-opps
109 - |
112 compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404";
113 #address-cells = <2>;
114 #size-cells = <2>;
117 #address-cells = <1>;
118 #size-cells = <0>;
122 compatible = "arm,cortex-a53";
124 enable-method = "psci";
125 cpu-idle-states = <&CPU_SLEEP_0>;
126 next-level-cache = <&L2_0>;
127 #cooling-cells = <2>;
129 operating-points-v2 = <&cpu_opp_table>;
130 power-domains = <&cpr>;
131 power-domain-names = "cpr";
136 compatible = "arm,cortex-a53";
138 enable-method = "psci";
139 cpu-idle-states = <&CPU_SLEEP_0>;
140 next-level-cache = <&L2_0>;
141 #cooling-cells = <2>;
143 operating-points-v2 = <&cpu_opp_table>;
144 power-domains = <&cpr>;
145 power-domain-names = "cpr";
150 compatible = "arm,cortex-a53";
152 enable-method = "psci";
153 cpu-idle-states = <&CPU_SLEEP_0>;
154 next-level-cache = <&L2_0>;
155 #cooling-cells = <2>;
157 operating-points-v2 = <&cpu_opp_table>;
158 power-domains = <&cpr>;
159 power-domain-names = "cpr";
164 compatible = "arm,cortex-a53";
166 enable-method = "psci";
167 cpu-idle-states = <&CPU_SLEEP_0>;
168 next-level-cache = <&L2_0>;
169 #cooling-cells = <2>;
171 operating-points-v2 = <&cpu_opp_table>;
172 power-domains = <&cpr>;
173 power-domain-names = "cpr";
177 cpu_opp_table: opp-table-cpu {
178 compatible = "operating-points-v2-kryo-cpu";
179 opp-shared;
181 opp-1094400000 {
182 opp-hz = /bits/ 64 <1094400000>;
183 required-opps = <&cpr_opp1>;
185 opp-1248000000 {
186 opp-hz = /bits/ 64 <1248000000>;
187 required-opps = <&cpr_opp2>;
189 opp-1401600000 {
190 opp-hz = /bits/ 64 <1401600000>;
191 required-opps = <&cpr_opp3>;
195 cpr_opp_table: opp-table-cpr {
196 compatible = "operating-points-v2-qcom-level";
199 opp-level = <1>;
200 qcom,opp-fuse-level = <1>;
203 opp-level = <2>;
204 qcom,opp-fuse-level = <2>;
207 opp-level = <3>;
208 qcom,opp-fuse-level = <3>;