Lines Matching +full:opp +full:- +full:supply
5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
32 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
37 compatible = "operating-points-v2";
38 opp-shared;
40 opp-598000000 {
41 opp-hz = /bits/ 64 <598000000>;
42 opp-microvolt = <1050000>;
45 opp-747500000 {
46 opp-hz = /bits/ 64 <747500000>;
47 opp-microvolt = <1050000>;
50 opp-1040000000 {
51 opp-hz = /bits/ 64 <1040000000>;
52 opp-microvolt = <1150000>;
55 opp-1196000000 {
56 opp-hz = /bits/ 64 <1196000000>;
57 opp-microvolt = <1200000>;
60 opp-1300000000 {
61 opp-hz = /bits/ 64 <1300000000>;
62 opp-microvolt = <1300000>;
68 compatible = "arm,cortex-a7";
72 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>;
78 compatible = "arm,cortex-a7";
80 operating-points-v2 = <&cpu_opp_table>;
84 compatible = "arm,cortex-a7";
86 operating-points-v2 = <&cpu_opp_table>;
90 compatible = "arm,cortex-a7";
92 operating-points-v2 = <&cpu_opp_table>;
97 compatible = "operating-points-v2";
98 opp-shared;
100 opp-507000000 {
101 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <859000>;
105 opp-702000000 {
106 opp-hz = /bits/ 64 <702000000>;
107 opp-microvolt = <908000>;
110 opp-1001000000 {
111 opp-hz = /bits/ 64 <1001000000>;
112 opp-microvolt = <983000>;
115 opp-1105000000 {
116 opp-hz = /bits/ 64 <1105000000>;
117 opp-microvolt = <1009000>;
120 opp-1183000000 {
121 opp-hz = /bits/ 64 <1183000000>;
122 opp-microvolt = <1028000>;
125 opp-1404000000 {
126 opp-hz = /bits/ 64 <1404000000>;
127 opp-microvolt = <1083000>;
130 opp-1508000000 {
131 opp-hz = /bits/ 64 <1508000000>;
132 opp-microvolt = <1109000>;
135 opp-1573000000 {
136 opp-hz = /bits/ 64 <1573000000>;
137 opp-microvolt = <1125000>;
142 compatible = "operating-points-v2";
143 opp-shared;
145 opp-507000000 {
146 opp-hz = /bits/ 64 <507000000>;
147 opp-microvolt = <828000>;
150 opp-702000000 {
151 opp-hz = /bits/ 64 <702000000>;
152 opp-microvolt = <867000>;
155 opp-1001000000 {
156 opp-hz = /bits/ 64 <1001000000>;
157 opp-microvolt = <927000>;
160 opp-1209000000 {
161 opp-hz = /bits/ 64 <1209000000>;
162 opp-microvolt = <968000>;
165 opp-1404000000 {
166 opp-hz = /bits/ 64 <1007000000>;
167 opp-microvolt = <1028000>;
170 opp-1612000000 {
171 opp-hz = /bits/ 64 <1612000000>;
172 opp-microvolt = <1049000>;
175 opp-1807000000 {
176 opp-hz = /bits/ 64 <1807000000>;
177 opp-microvolt = <1089000>;
180 opp-1989000000 {
181 opp-hz = /bits/ 64 <1989000000>;
182 opp-microvolt = <1125000>;
188 compatible = "arm,cortex-a53";
190 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_0>;
194 clock-names = "cpu", "intermediate";
195 operating-points-v2 = <&cpu_opp_table_a>;
200 compatible = "arm,cortex-a53";
202 enable-method = "psci";
203 cpu-idle-states = <&CPU_SLEEP_0>;
206 clock-names = "cpu", "intermediate";
207 operating-points-v2 = <&cpu_opp_table_a>;
212 compatible = "arm,cortex-a72";
214 enable-method = "psci";
215 cpu-idle-states = <&CPU_SLEEP_0>;
218 clock-names = "cpu", "intermediate";
219 operating-points-v2 = <&cpu_opp_table_b>;
224 compatible = "arm,cortex-a72";
226 enable-method = "psci";
227 cpu-idle-states = <&CPU_SLEEP_0>;
230 clock-names = "cpu", "intermediate";
231 operating-points-v2 = <&cpu_opp_table_b>;
235 proc-supply = <&mt6397_vpca15_reg>;
239 proc-supply = <&mt6397_vpca15_reg>;
243 proc-supply = <&da9211_vcpu_reg>;
244 sram-supply = <&mt6397_vsramca7_reg>;
248 proc-supply = <&da9211_vcpu_reg>;
249 sram-supply = <&mt6397_vsramca7_reg>;