Lines Matching +full:opp +full:- +full:600000000
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
22 - enum:
23 - apple,t8103-cluster-cpufreq
24 - apple,t8112-cluster-cpufreq
25 - const: apple,cluster-cpufreq
26 - items:
27 - const: apple,t6000-cluster-cpufreq
28 - const: apple,t8103-cluster-cpufreq
29 - const: apple,cluster-cpufreq
34 '#performance-domain-cells':
38 - compatible
39 - reg
40 - '#performance-domain-cells'
45 - |
47 // with two p-states per domain.
48 // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
50 #address-cells = <2>;
51 #size-cells = <0>;
57 operating-points-v2 = <&ecluster_opp>;
58 performance-domains = <&cpufreq_e>;
65 operating-points-v2 = <&pcluster_opp>;
66 performance-domains = <&cpufreq_p>;
70 ecluster_opp: opp-table-0 {
71 compatible = "operating-points-v2";
72 opp-shared;
75 opp-hz = /bits/ 64 <600000000>;
76 opp-level = <1>;
77 clock-latency-ns = <7500>;
80 opp-hz = /bits/ 64 <972000000>;
81 opp-level = <2>;
82 clock-latency-ns = <22000>;
86 pcluster_opp: opp-table-1 {
87 compatible = "operating-points-v2";
88 opp-shared;
91 opp-hz = /bits/ 64 <600000000>;
92 opp-level = <1>;
93 clock-latency-ns = <8000>;
96 opp-hz = /bits/ 64 <828000000>;
97 opp-level = <2>;
98 clock-latency-ns = <19000>;
103 #address-cells = <2>;
104 #size-cells = <2>;
106 cpufreq_e: performance-controller@210e20000 {
107 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
109 #performance-domain-cells = <0>;
112 cpufreq_p: performance-controller@211e20000 {
113 compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
115 #performance-domain-cells = <0>;