Lines Matching +full:composite +full:- +full:in
3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped multiplexer with multiple input clock signals or
10 By default the "clocks" property lists the parents in the same order
15 results in programming the register as follows:
24 "index-starts-at-one" modified the scheme as follows:
32 the number of bits to shift the control field in the register can be
36 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
39 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
40 - #clock-cells : from common clock binding; shall be set to 0.
41 - clocks : link phandles of parent clocks
42 - reg : register offset for register controlling adjustable mux
45 - clock-output-names : from common clock binding.
46 - ti,bit-shift : number of bits to shift the bit-mask, defaults to
48 - ti,index-starts-at-one : valid input select programming starts at 1, not
50 - ti,set-rate-parent : clk_set_rate is propagated to parent clock,
51 not supported by the composite-mux-clock subtype
52 - ti,latch-bit : latch the mux value to HW, only needed if the register
59 #clock-cells = <0>;
60 compatible = "ti,mux-clock";
63 ti,index-starts-at-one;
67 #clock-cells = <0>;
68 compatible = "ti,mux-clock";
70 ti,bit-shift = <24>;
75 #clock-cells = <0>;
76 compatible = "ti,composite-mux-clock";
78 ti,bit-shift = <4>;