Lines Matching +full:composite +full:- +full:in

3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped adjustable clock rate divider that does not gate and has
17 ti,index-starts-at-one - valid divisor values start at 1, not the default
24 ti,index-power-of-two - valid divisor values are powers of two.  E.g:
41 Any zero value in this array means the corresponding bit-value is invalid
52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - #clock-cells : from common clock binding; shall be set to 0.
58 - clocks : link to phandle of parent clock
59 - reg : offset for register controlling adjustable divider
62 - clock-output-names : from common clock binding.
63 - ti,dividers : array of integers defining divisors
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
65 - ti,min-div : min divisor for dividing the input clock rate, only
67 - ti,max-div : max divisor for dividing the input clock rate, only needed
69 - ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
71 - ti,index-power-of-two : valid divisor programming must be a power of two,
73 - ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
75 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
77 - ti,set-rate-parent : clk_set_rate is propagated to parent
78 - ti,latch-bit : latch the divider value to HW, only needed if the register
84 	#clock-cells = <0>;
85 	compatible = "ti,divider-clock";
87 	ti,max-div = <127>;
89 	ti,index-starts-at-one;
93 	#clock-cells = <0>;
94 	compatible = "ti,divider-clock";
96 	ti,bit-shift = <24>;
98 	ti,max-div = <2>;
102 	#clock-cells = <0>;
103 	compatible = "ti,composite-divider-clock";
105 	ti,max-div = <31>;
107 	ti,index-starts-at-one;
111 	#clock-cells = <0>;
112 	compatible = "ti,composite-divider-clock";
114 	ti,bit-shift = <8>;