Lines Matching +full:sync +full:- +full:in +full:- +full:gpios
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
40 - description: PLL2 reference clock.
42 clock-names:
44 - const: oscin
46 reset-gpios:
49 ti,spi-4wire-rdbk:
60 ti,vco-hz:
61 description: Optional to set VCO frequency of the PLL in Hertz.
63 ti,sysref-ddly:
70 ti,sysref-mux:
74 Normal SYNC 0
75 Re-clocked 1
82 ti,sync-mode:
83 description: SYNC pin configuration.
88 ti,sysref-pulse-count:
90 Number of SYSREF pulses to send when SYSREF is not in continuous mode.
96 "@[0-9a-d]+$":
108 ti,clkout-fmt:
132 ti,clkout-sysref:
138 - reg
143 - compatible
144 - reg
145 - '#clock-cells'
146 - clocks
147 - clock-names
152 - |
155 compatible = "fixed-clock";
157 #clock-cells = <0>;
158 clock-frequency = <122880000>;
159 clock-output-names = "lmk04832-oscin";
164 #address-cells = <1>;
165 #size-cells = <0>;
167 lmk04832: clock-controller@0 {
168 #address-cells = <1>;
169 #size-cells = <0>;
174 spi-max-frequency = <781250>;
176 reset-gpios = <&gpio_lmk 0 0 0>;
178 #clock-cells = <1>;
180 clock-names = "oscin";
182 ti,spi-4wire-rdbk = <0>;
183 ti,vco-hz = <2457600000>;
185 assigned-clocks =
191 assigned-clock-rates =
200 ti,clkout-fmt = <0x01>; // LVDS
205 ti,clkout-fmt = <0x01>; // LVDS
206 ti,clkout-sysref;