Lines Matching +full:pll +full:- +full:mode

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Alexander Stein <alexander.stein@ew.tq-group.com>
15   - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16   - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17   - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18   - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23       - ti,cdce913
24       - ti,cdce925
25       - ti,cdce937
26       - ti,cdce949
33       - description: fixed parent clock
35   "#clock-cells":
38   vdd-supply:
41   vddout-supply:
44       non-L variant: 2.5V or 3.3V for
47   xtal-load-pf:
50       Crystal load-capacitor value to fine-tune performance on a
54   "^PLL[1-4]$":
63       spread-spectrum:
65         description: SSC mode as defined in the data sheet
67       spread-spectrum-center:
70           Use "centered" mode instead of "max" mode. When
76   - compatible
77   - reg
78   - clocks
79   - "#clock-cells"
84   - |
86         #address-cells = <1>;
87         #size-cells = <0>;
89         cdce925: clock-controller@64 {
93             #clock-cells = <1>;
94             xtal-load-pf = <5>;
95             vdd-supply = <&reg_1v8>;
96             vddout-supply = <&reg_3v3>;
97             /* PLL options to get SSC 1% centered */
99                 spread-spectrum = <4>;
100                 spread-spectrum-center;