Lines Matching +full:pll +full:- +full:mode
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
21 - clocks: Points to a fixed parent clock that provides the input frequency.
22 - #clock-cells: From common clock bindings: Shall be 1.
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
27 - vdd-supply: A regulator node for Vdd
28 - vddout-supply: A regulator node for Vddout
32 - spread-spectrum: SSC mode as defined in the data sheet.
33 - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
44 #clock-cells = <1>;
45 xtal-load-pf = <5>;
46 vdd-supply = <&1v8-reg>;
47 vddout-supply = <&3v3-reg>;
48 /* PLL options to get SSC 1% centered */
50 spread-spectrum = <4>;
51 spread-spectrum-center;