Lines Matching +full:stm32f42xx +full:- +full:rcc
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
24 - high speed external clock signal (HSE)
25 - external I2S clock (I2S_CKIN)
29 rcc: rcc@40023800 {
30 #reset-cells = <1>;
31 #clock-cells = <2>
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
50 human-readble format.
53 - include/dt-bindings/mfd/stm32f4-rcc.h
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
76 2 CLK_LSI (low-power clock source)
77 3 CLK_LSE (generated from a 32.768 kHz low-speed external
80 5 CLK_RTC (real-time clock)
83 8 CLK_LCD (LCD-TFT)
92 16 CLK_HDMI_CEC (HDMI-CEC clock)
93 17 CLK_SPDIF (SPDIF-Rx clock)
117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
127 The index is the bit number within the RCC registers bank, starting from RCC
137 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;