Lines Matching +full:pll +full:-

1 Binding for the AXS10X Generic PLL clock
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9   "snps,axs10x-arc-pll-clock"
10   "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 	input-clk: input-clk {
18 		clock-frequency = <33333333>;
19 		compatible = "fixed-clock";
20 		#clock-cells = <0>;
23 	core-clk: core-clk@80 {
24 		compatible = "snps,axs10x-arc-pll-clock";
26 		#clock-cells = <0>;
27 		clocks = <&input-clk>;