Lines Matching refs:source

30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31   to overwrite clock source of pll A (number=0) or B (number=1).
43 - silabs,clock-source: source clock of the output divider stage N, shall be
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
82 		/* connect xtal input as source of pll0 and pll1 */
83 		silabs,pll-source = <0 0>, <1 0>;
88 		 * - pll0 as clock source of multisynth0
89 		 * - multisynth0 as clock source of output divider
96 			silabs,multisynth-source = <0>;
97 			silabs,clock-source = <0>;
105 		 * - pll1 as clock source of multisynth1
106 		 * - multisynth1 as clock source of output divider
112 			silabs,multisynth-source = <1>;
113 			silabs,clock-source = <0>;
119 		 * - xtal as clock source of output divider
123 			silabs,clock-source = <2>;