Lines Matching +full:exynos5433 +full:- +full:decon
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "oscclk" - PLL input clock from XXTI
21 include/dt-bindings/clock/exynos5433.h header.
29 - samsung,exynos5433-cmu-top
31 - samsung,exynos5433-cmu-cpif
33 - samsung,exynos5433-cmu-mif
36 - samsung,exynos5433-cmu-peric
38 - samsung,exynos5433-cmu-peris
40 - samsung,exynos5433-cmu-fsys
41 - samsung,exynos5433-cmu-g2d
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
43 - samsung,exynos5433-cmu-disp
44 - samsung,exynos5433-cmu-aud
45 - samsung,exynos5433-cmu-bus0
46 - samsung,exynos5433-cmu-bus1
47 - samsung,exynos5433-cmu-bus2
48 - samsung,exynos5433-cmu-g3d
49 - samsung,exynos5433-cmu-gscl
50 - samsung,exynos5433-cmu-apollo
51 # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
53 - samsung,exynos5433-cmu-atlas
56 - samsung,exynos5433-cmu-mscl
57 - samsung,exynos5433-cmu-mfc
58 - samsung,exynos5433-cmu-hevc
59 # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
60 - samsung,exynos5433-cmu-isp
63 - samsung,exynos5433-cmu-cam0
65 # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
66 - samsung,exynos5433-cmu-cam1
69 - samsung,exynos5433-cmu-imem
75 clock-names:
79 "#clock-cells":
82 power-domains:
89 - compatible
90 - "#clock-cells"
91 - reg
94 - if:
98 const: samsung,exynos5433-cmu-top
104 clock-names:
106 - const: oscclk
107 - const: sclk_mphy_pll
108 - const: sclk_mfc_pll
109 - const: sclk_bus_pll
111 - clock-names
112 - clocks
114 - if:
118 const: samsung,exynos5433-cmu-cpif
124 clock-names:
126 - const: oscclk
128 - clock-names
129 - clocks
131 - if:
135 const: samsung,exynos5433-cmu-mif
141 clock-names:
143 - const: oscclk
144 - const: sclk_mphy_pll
146 - clock-names
147 - clocks
149 - if:
153 const: samsung,exynos5433-cmu-fsys
159 clock-names:
161 - const: oscclk
162 - const: sclk_ufs_mphy
163 - const: aclk_fsys_200
164 - const: sclk_pcie_100_fsys
165 - const: sclk_ufsunipro_fsys
166 - const: sclk_mmc2_fsys
167 - const: sclk_mmc1_fsys
168 - const: sclk_mmc0_fsys
169 - const: sclk_usbhost30_fsys
170 - const: sclk_usbdrd30_fsys
172 - clock-names
173 - clocks
175 - if:
179 const: samsung,exynos5433-cmu-g2d
185 clock-names:
187 - const: oscclk
188 - const: aclk_g2d_266
189 - const: aclk_g2d_400
191 - clock-names
192 - clocks
194 - if:
198 const: samsung,exynos5433-cmu-disp
204 clock-names:
206 - const: oscclk
207 - const: sclk_dsim1_disp
208 - const: sclk_dsim0_disp
209 - const: sclk_dsd_disp
210 - const: sclk_decon_tv_eclk_disp
211 - const: sclk_decon_vclk_disp
212 - const: sclk_decon_eclk_disp
213 - const: sclk_decon_tv_vclk_disp
214 - const: aclk_disp_333
216 - clock-names
217 - clocks
219 - if:
223 const: samsung,exynos5433-cmu-aud
229 clock-names:
231 - const: oscclk
232 - const: fout_aud_pll
234 - clock-names
235 - clocks
237 - if:
241 const: samsung,exynos5433-cmu-bus0
247 clock-names:
249 - const: aclk_bus0_400
251 - clock-names
252 - clocks
254 - if:
258 const: samsung,exynos5433-cmu-bus1
264 clock-names:
266 - const: aclk_bus1_400
268 - clock-names
269 - clocks
271 - if:
275 const: samsung,exynos5433-cmu-bus2
281 clock-names:
283 - const: oscclk
284 - const: aclk_bus2_400
286 - clock-names
287 - clocks
289 - if:
293 const: samsung,exynos5433-cmu-g3d
299 clock-names:
301 - const: oscclk
302 - const: aclk_g3d_400
304 - clock-names
305 - clocks
307 - if:
311 const: samsung,exynos5433-cmu-gscl
317 clock-names:
319 - const: oscclk
320 - const: aclk_gscl_111
321 - const: aclk_gscl_333
323 - clock-names
324 - clocks
326 - if:
330 const: samsung,exynos5433-cmu-apollo
336 clock-names:
338 - const: oscclk
339 - const: sclk_bus_pll_apollo
341 - clock-names
342 - clocks
344 - if:
348 const: samsung,exynos5433-cmu-atlas
354 clock-names:
356 - const: oscclk
357 - const: sclk_bus_pll_atlas
359 - clock-names
360 - clocks
362 - if:
366 const: samsung,exynos5433-cmu-mscl
372 clock-names:
374 - const: oscclk
375 - const: sclk_jpeg_mscl
376 - const: aclk_mscl_400
378 - clock-names
379 - clocks
381 - if:
385 const: samsung,exynos5433-cmu-mfc
391 clock-names:
393 - const: oscclk
394 - const: aclk_mfc_400
396 - clock-names
397 - clocks
399 - if:
403 const: samsung,exynos5433-cmu-hevc
409 clock-names:
411 - const: oscclk
412 - const: aclk_hevc_400
414 - clock-names
415 - clocks
417 - if:
421 const: samsung,exynos5433-cmu-isp
427 clock-names:
429 - const: oscclk
430 - const: aclk_isp_dis_400
431 - const: aclk_isp_400
433 - clock-names
434 - clocks
436 - if:
440 const: samsung,exynos5433-cmu-cam0
446 clock-names:
448 - const: oscclk
449 - const: aclk_cam0_333
450 - const: aclk_cam0_400
451 - const: aclk_cam0_552
453 - clock-names
454 - clocks
456 - if:
460 const: samsung,exynos5433-cmu-cam1
466 clock-names:
468 - const: oscclk
469 - const: sclk_isp_uart_cam1
470 - const: sclk_isp_spi1_cam1
471 - const: sclk_isp_spi0_cam1
472 - const: aclk_cam1_333
473 - const: aclk_cam1_400
474 - const: aclk_cam1_552
476 - clock-names
477 - clocks
479 - if:
483 const: samsung,exynos5433-cmu-imem
489 clock-names:
491 - const: oscclk
492 - const: aclk_imem_sssx_266
493 - const: aclk_imem_266
494 - const: aclk_imem_200
496 - clock-names
497 - clocks
502 - |
503 #include <dt-bindings/clock/exynos5433.h>
505 compatible = "fixed-clock";
506 clock-output-names = "oscclk";
507 #clock-cells = <0>;
508 clock-frequency = <24000000>;
511 clock-controller@10030000 {
512 compatible = "samsung,exynos5433-cmu-top";
514 #clock-cells = <1>;
516 clock-names = "oscclk",