Lines Matching +full:r8a7740 +full:- +full:cpg +full:- +full:clocks

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas CPG DIV6 Clock
10   - Geert Uytterhoeven <geert+renesas@glider.be>
13   The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14   Generator (CPG). Their clock input is divided by a configurable factor from 1
20       - enum:
21           - renesas,r8a73a4-div6-clock # R-Mobile APE6
22           - renesas,r8a7740-div6-clock # R-Mobile A1
23           - renesas,sh73a0-div6-clock  # SH-Mobile AG5
24       - const: renesas,cpg-div6-clock
29   clocks:
31       - maxItems: 1
32       - maxItems: 4
33       - maxItems: 8
35       For clocks with multiple parents, invalid settings must be specified as
38   '#clock-cells':
41   clock-output-names: true
44   - compatible
45   - reg
46   - clocks
47   - '#clock-cells'
52   - |
53     #include <dt-bindings/clock/r8a73a4-clock.h>
56             compatible = "renesas,r8a73a4-cpg-clocks";
58             clocks = <&extal1_clk>, <&extal2_clk>;
59             #clock-cells = <1>;
60             clock-output-names = "main", "pll0", "pll1", "pll2",
67             compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
69             clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
71             #clock-cells = <0>;