Lines Matching +full:sm4450 +full:- +full:dispcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM4450
10 - Ajit Pandey <quic_ajipan@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
15 domains on SM4450
17 See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
21 const: qcom,sm4450-dispcc
28 - description: Board XO source
29 - description: Board active XO source
30 - description: Display AHB clock source from GCC
31 - description: sleep clock source
32 - description: Byte clock from DSI PHY0
33 - description: Pixel clock from DSI PHY0
35 '#clock-cells':
38 '#reset-cells':
41 '#power-domain-cells':
45 - compatible
46 - reg
47 - clocks
48 - '#clock-cells'
49 - '#reset-cells'
50 - '#power-domain-cells'
55 - |
56 #include <dt-bindings/clock/qcom,rpmh.h>
57 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
58 clock-controller@af00000 {
59 compatible = "qcom,sm4450-dispcc";
67 #clock-cells = <1>;
68 #reset-cells = <1>;
69 #power-domain-cells = <1>;