Lines Matching +full:1 +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm multimedia clock control module provides the clocks, resets and
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
25 - qcom,mmcc-msm8974
26 - qcom,mmcc-msm8992
27 - qcom,mmcc-msm8994
28 - qcom,mmcc-msm8996
29 - qcom,mmcc-msm8998
30 - qcom,mmcc-sdm630
31 - qcom,mmcc-sdm660
37 clock-names:
41 vdd-gfx-supply:
46 - compatible
47 - '#power-domain-cells'
50 - $ref: qcom,gcc.yaml#
51 - if:
56 - qcom,mmcc-apq8064
57 - qcom,mmcc-msm8960
63 - description: Board PXO source
64 - description: PLL 3 clock
65 - description: PLL 3 Vote clock
66 - description: DSI phy instance 1 dsi clock
67 - description: DSI phy instance 1 byte clock
68 - description: DSI phy instance 2 dsi clock
69 - description: DSI phy instance 2 byte clock
70 - description: HDMI phy PLL clock
71 - description: LVDS PLL clock
73 clock-names:
76 - const: pxo
77 - const: pll3
78 - const: pll8_vote
79 - const: dsi1pll
80 - const: dsi1pllbyte
81 - const: dsi2pll
82 - const: dsi2pllbyte
83 - const: hdmipll
84 - const: lvdspll
86 - if:
91 - qcom,mmcc-msm8226
96 - description: Board XO source
97 - description: MMSS GPLL0 voted clock
98 - description: GPLL0 voted clock
99 - description: GPLL1 voted clock
100 - description: GFX3D clock source
101 - description: DSI phy instance 0 dsi clock
102 - description: DSI phy instance 0 byte clock
104 clock-names:
106 - const: xo
107 - const: mmss_gpll0_vote
108 - const: gpll0_vote
109 - const: gpll1_vote
110 - const: gfx3d_clk_src
111 - const: dsi0pll
112 - const: dsi0pllbyte
114 - if:
119 - qcom,mmcc-msm8974
124 - description: Board XO source
125 - description: MMSS GPLL0 voted clock
126 - description: GPLL0 voted clock
127 - description: GPLL1 voted clock
128 - description: GFX3D clock source
129 - description: DSI phy instance 0 dsi clock
130 - description: DSI phy instance 0 byte clock
131 - description: DSI phy instance 1 dsi clock
132 - description: DSI phy instance 1 byte clock
133 - description: HDMI phy PLL clock
134 - description: eDP phy PLL link clock
135 - description: eDP phy PLL vco clock
137 clock-names:
139 - const: xo
140 - const: mmss_gpll0_vote
141 - const: gpll0_vote
142 - const: gpll1_vote
143 - const: gfx3d_clk_src
144 - const: dsi0pll
145 - const: dsi0pllbyte
146 - const: dsi1pll
147 - const: dsi1pllbyte
148 - const: hdmipll
149 - const: edp_link_clk
150 - const: edp_vco_div
152 - if:
157 - qcom,mmcc-apq8084
162 - description: Board XO source
163 - description: Board sleep source
164 - description: MMSS GPLL0 voted clock
165 - description: GPLL0 clock
166 - description: GPLL0 voted clock
167 - description: GPLL1 clock
168 - description: DSI phy instance 0 dsi clock
169 - description: DSI phy instance 0 byte clock
170 - description: DSI phy instance 1 dsi clock
171 - description: DSI phy instance 1 byte clock
172 - description: HDMI phy PLL clock
173 - description: eDP phy PLL link clock
174 - description: eDP phy PLL vco clock
176 clock-names:
178 - const: xo
179 - const: sleep_clk
180 - const: mmss_gpll0_vote
181 - const: gpll0
182 - const: gpll0_vote
183 - const: gpll1
184 - const: dsi0pll
185 - const: dsi0pllbyte
186 - const: dsi1pll
187 - const: dsi1pllbyte
188 - const: hdmipll
189 - const: edp_link_clk
190 - const: edp_vco_div
192 - if:
197 - qcom,mmcc-msm8994
198 - qcom,mmcc-msm8998
199 - qcom,mmcc-sdm630
200 - qcom,mmcc-sdm660
203 - clocks
204 - clock-names
206 - if:
210 const: qcom,mmcc-msm8994
215 - description: Board XO source
216 - description: Global PLL 0 clock
217 - description: MMSS NoC AHB clock
218 - description: GFX3D clock
219 - description: DSI phy instance 0 dsi clock
220 - description: DSI phy instance 0 byte clock
221 - description: DSI phy instance 1 dsi clock
222 - description: DSI phy instance 1 byte clock
223 - description: HDMI phy PLL clock
225 clock-names:
227 - const: xo
228 - const: gpll0
229 - const: mmssnoc_ahb
230 - const: oxili_gfx3d_clk_src
231 - const: dsi0pll
232 - const: dsi0pllbyte
233 - const: dsi1pll
234 - const: dsi1pllbyte
235 - const: hdmipll
237 - if:
241 const: qcom,mmcc-msm8996
246 - description: Board XO source
247 - description: Global PLL 0 clock
248 - description: MMSS NoC AHB clock
249 - description: DSI phy instance 0 dsi clock
250 - description: DSI phy instance 0 byte clock
251 - description: DSI phy instance 1 dsi clock
252 - description: DSI phy instance 1 byte clock
253 - description: HDMI phy PLL clock
255 clock-names:
257 - const: xo
258 - const: gpll0
259 - const: gcc_mmss_noc_cfg_ahb_clk
260 - const: dsi0pll
261 - const: dsi0pllbyte
262 - const: dsi1pll
263 - const: dsi1pllbyte
264 - const: hdmipll
266 - if:
270 const: qcom,mmcc-msm8998
275 - description: Board XO source
276 - description: Global PLL 0 clock
277 - description: DSI phy instance 0 dsi clock
278 - description: DSI phy instance 0 byte clock
279 - description: DSI phy instance 1 dsi clock
280 - description: DSI phy instance 1 byte clock
281 - description: HDMI phy PLL clock
282 - description: DisplayPort phy PLL link clock
283 - description: DisplayPort phy PLL vco clock
284 - description: Global PLL 0 DIV clock
286 clock-names:
288 - const: xo
289 - const: gpll0
290 - const: dsi0dsi
291 - const: dsi0byte
292 - const: dsi1dsi
293 - const: dsi1byte
294 - const: hdmipll
295 - const: dplink
296 - const: dpvco
297 - const: gpll0_div
299 - if:
304 - qcom,mmcc-sdm630
305 - qcom,mmcc-sdm660
310 - description: Board XO source
311 - description: Board sleep source
312 - description: Global PLL 0 clock
313 - description: Global PLL 0 DIV clock
314 - description: DSI phy instance 0 dsi clock
315 - description: DSI phy instance 0 byte clock
316 - description: DSI phy instance 1 dsi clock
317 - description: DSI phy instance 1 byte clock
318 - description: DisplayPort phy PLL link clock
319 - description: DisplayPort phy PLL vco clock
321 clock-names:
323 - const: xo
324 - const: sleep_clk
325 - const: gpll0
326 - const: gpll0_div
327 - const: dsi0pll
328 - const: dsi0pllbyte
329 - const: dsi1pll
330 - const: dsi1pllbyte
331 - const: dp_link_2x_clk_divsel_five
332 - const: dp_vco_divided_clk_src_mux
338 - |
339 clock-controller@4000000 {
340 compatible = "qcom,mmcc-msm8960";
342 #clock-cells = <1>;
343 #reset-cells = <1>;
344 #power-domain-cells = <1>;