Lines Matching +full:sm8350 +full:- +full:rpmhpd

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
10   - Jonathan Marek <jonathan@marek.ca>
14   domains on SM8150/SM8250/SM8350.
17     include/dt-bindings/clock/qcom,dispcc-sm8150.h
18     include/dt-bindings/clock/qcom,dispcc-sm8250.h
19     include/dt-bindings/clock/qcom,dispcc-sm8350.h
24       - qcom,sc8180x-dispcc
25       - qcom,sm8150-dispcc
26       - qcom,sm8250-dispcc
27       - qcom,sm8350-dispcc
31       - description: Board XO source
32       - description: Byte clock from DSI PHY0
33       - description: Pixel clock from DSI PHY0
34       - description: Byte clock from DSI PHY1
35       - description: Pixel clock from DSI PHY1
36       - description: Link clock from DP PHY
37       - description: VCO DIV clock from DP PHY
39   clock-names:
41       - const: bi_tcxo
42       - const: dsi0_phy_pll_out_byteclk
43       - const: dsi0_phy_pll_out_dsiclk
44       - const: dsi1_phy_pll_out_byteclk
45       - const: dsi1_phy_pll_out_dsiclk
46       - const: dp_phy_pll_link_clk
47       - const: dp_phy_pll_vco_div_clk
49   '#clock-cells':
52   '#reset-cells':
55   '#power-domain-cells':
61   power-domains:
66   required-opps:
72   - compatible
73   - reg
74   - clocks
75   - clock-names
76   - '#clock-cells'
77   - '#reset-cells'
78   - '#power-domain-cells'
83   - |
84     #include <dt-bindings/clock/qcom,rpmh.h>
85     #include <dt-bindings/power/qcom,rpmhpd.h>
86     clock-controller@af00000 {
87       compatible = "qcom,sm8250-dispcc";
96       clock-names = "bi_tcxo",
103       #clock-cells = <1>;
104       #reset-cells = <1>;
105       #power-domain-cells = <1>;
106       power-domains = <&rpmhpd RPMHPD_MMCX>;
107       required-opps = <&rpmhpd_opp_low_svs>;