Lines Matching +full:tegra20 +full:- +full:car
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
31 - nvidia,tegra20-car
32 - nvidia,tegra30-car
33 - nvidia,tegra114-car
34 - nvidia,tegra210-car
39 '#clock-cells':
42 "#reset-cells":
46 "^(sclk)|(pll-[cem])$":
51 - nvidia,tegra20-sclk
52 - nvidia,tegra30-sclk
53 - nvidia,tegra30-pllc
54 - nvidia,tegra30-plle
55 - nvidia,tegra30-pllm
57 operating-points-v2: true
61 - description: node's clock
63 power-domains:
68 - compatible
69 - operating-points-v2
70 - clocks
71 - power-domains
76 - compatible
77 - reg
78 - '#clock-cells'
79 - "#reset-cells"
84 - |
85 #include <dt-bindings/clock/tegra20-car.h>
87 car: clock-controller@60006000 {
88 compatible = "nvidia,tegra20-car";
90 #clock-cells = <1>;
91 #reset-cells = <1>;
94 compatible = "nvidia,tegra20-sclk";
95 operating-points-v2 = <&opp_table>;
97 power-domains = <&domain>;