Lines Matching +full:pwm +full:- +full:clock
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
20 - look-up table RAM for voltage register values.
21 - interrupts: Should contain the DFLL block interrupt.
22 - clocks: Must contain an entry for each entry in clock-names.
23 See clock-bindings.txt for details.
24 - clock-names: Must include the following entries:
25 - soc: Clock source for the DFLL control logic.
26 - ref: The closed loop reference clock
27 - i2c: Clock source for the integrated I2C master.
28 - resets: Must contain an entry for each entry in reset-names.
30 - reset-names: Must include the following entries:
31 - dvco: Reset control for the DFLL DVCO.
32 - #clock-cells: Must be 0.
33 - clock-output-names: Name of the clock output.
34 - vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
39 - nvidia,sample-rate: Sample rate of the DFLL control loop.
40 - nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
41 - nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
42 - nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
43 - nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
44 - nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
47 - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
50 - nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
53 - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
55 Required properties for PWM mode:
56 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
57 - nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
58 control is disabled and the PWM output is tristated. Note that this voltage is
60 - nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
61 is enabled and PWM output is low. Hence, this is the minimum output voltage
62 that the regulator supports when PWM control is enabled.
63 - nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
65 duty cycle would be: nvidia,pwm-min-microvolts +
66 nvidia,pwm-voltage-step-microvolts * 2.
67 - pinctrl-0: I/O pad configuration when PWM control is enabled.
68 - pinctrl-1: I/O pad configuration when PWM control is disabled.
69 - pinctrl-names: must include the following entries:
70 - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
71 - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
75 clock@70110000 {
76 compatible = "nvidia,tegra124-dfll";
80 <0 0x70110200 0 0x100>; /* Look-up table RAM */
85 clock-names = "soc", "ref", "i2c";
87 reset-names = "dvco";
88 #clock-cells = <0>;
89 clock-output-names = "dfllCPU_out";
90 vdd-cpu-supply = <&vdd_cpu>;
92 nvidia,sample-rate = <12500>;
93 nvidia,droop-ctrl = <0x00000f00>;
94 nvidia,force-mode = <1>;
99 nvidia,i2c-fs-rate = <400000>;
102 Example for PWM:
104 clock@70110000 {
105 compatible = "nvidia,tegra124-dfll";
109 <0 0x70110200 0 0x100>; /* Look-up table RAM */
114 clock-names = "soc", "ref", "i2c";
116 reset-names = "dvco";
117 #clock-cells = <0>;
118 clock-output-names = "dfllCPU_out";
120 nvidia,sample-rate = <25000>;
121 nvidia,droop-ctrl = <0x00000f00>;
122 nvidia,force-mode = <1>;
127 nvidia,pwm-min-microvolts = <708000>; /* 708mV */
128 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
129 nvidia,pwm-to-pmic;
130 nvidia,pwm-tristate-microvolts = <1000000>;
131 nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
133 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
134 pinctrl-0 = <&dvfs_pwm_active_state>;
135 pinctrl-1 = <&dvfs_pwm_inactive_state>;
139 * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml