Lines Matching +full:system +full:- +full:management

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - A.s. Dong <aisheng.dong@nxp.com>
13   i.MX7ULP Clock functions are under joint control of the System
19   domains, such as the System Oscillator clock, the Slow IRC (SIRC),
21   management are separated and contained within each domain.
23   M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24   A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
34   See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
40       - fsl,imx7ulp-pcc2
41       - fsl,imx7ulp-pcc3
46   '#clock-cells':
51       - description: nic1 bus clock
52       - description: nic1 clock
53       - description: ddr clock
54       - description: apll pfd2
55       - description: apll pfd1
56       - description: apll pfd0
57       - description: usb pll
58       - description: system osc bus clock
59       - description: fast internal reference clock bus
60       - description: rtc osc
61       - description: system pll bus clock
63   clock-names:
65       - const: nic1_bus_clk
66       - const: nic1_clk
67       - const: ddr_clk
68       - const: apll_pfd2
69       - const: apll_pfd1
70       - const: apll_pfd0
71       - const: upll
72       - const: sosc_bus_clk
73       - const: firc_bus_clk
74       - const: rosc
75       - const: spll_bus_clk
78   - compatible
79   - reg
80   - '#clock-cells'
81   - clocks
82   - clock-names
87   - |
88     #include <dt-bindings/clock/imx7ulp-clock.h>
89     #include <dt-bindings/interrupt-controller/arm-gic.h>
91     clock-controller@403f0000 {
92         compatible = "fsl,imx7ulp-pcc2";
94         #clock-cells = <1>;
106          clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",