Lines Matching +full:imx7ulp +full:- +full:clock

1 * Clock bindings for Freescale i.MX7ULP
3 i.MX7ULP Clock functions are under joint control of the System
4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
8 and A7 domain. Except for a few clock sources shared between two
9 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
10 and and the Fast IRC clock (FIRCLK), clock sources and clock
13 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
14 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
16 Note: this binding doc is only for A7 clock domain.
18 System Clock Generation (SCG) modules:
19 ---------------------------------------------------------------------
20 The System Clock Generation (SCG) is responsible for clock generation
22 include: clock reference selection, generation of clock used to derive
25 clock gating mode.
29 - compatible:	Should be "fsl,imx7ulp-scg1".
30 - reg : 	Should contain registers location and length.
31 - #clock-cells:	Should be <1>.
32 - clocks:	Should contain the fixed input clocks.
33 - clock-names:  Should contain the following clock names:
36 Peripheral Clock Control (PCC) modules:
37 ---------------------------------------------------------------------
38 The Peripheral Clock Control (PCC) is responsible for clock selection,
39 optional division and clock gating mode for peripherals in their
43 - compatible:	Should be one of:
44 		  "fsl,imx7ulp-pcc2",
45 		  "fsl,imx7ulp-pcc3".
46 - reg : 	Should contain registers location and length.
47 - #clock-cells:	Should be <1>.
48 - clocks:	Should contain the fixed input clocks.
49 - clock-names:  Should contain the following clock names:
54 The clock consumer should specify the desired clock by having the clock
56 See include/dt-bindings/clock/imx7ulp-clock.h
57 for the full list of i.MX7ULP clock IDs of each module.
61 #include <dt-bindings/clock/imx7ulp-clock.h>
64 	compatible = "fsl,imx7ulp-scg1;
68 	clock-names = "rosc", "sosc", "sirc",
70 	#clock-cells = <1>;
74 	compatible = "fsl,imx7ulp-pcc2";
76 	#clock-cells = <1>;
88 	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
95 	compatible = "fsl,imx7ulp-usdhc";
101 	clock-names ="ipg", "ahb", "per";
102 	bus-width = <4>;